Cascaded Arithmetic Units for Parallel Image Processing
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Solution Overview
Problem
Existing image processing systems face performance issues due to memory limitations, where external memory solutions reduce calculation speed and upgrading hardware increases costs, making it difficult to efficiently process large amounts of image data.
Innovation Solution
The implementation of a cascaded architecture using two arithmetic units connected by a serial transceiver, which segments original images into sub-images, performs convolution operations in parallel, and synthesizes results without relying on external memory, allowing for efficient processing of large image data without the need for high-capacity, high-cost hardware upgrades.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If external memory is used to extend memory capacity, then the memory capacity is improved, but the calculation speed deteriorates
Solution Approach 1:
The original image is segmented into multiple sub-images that can be processed in parallel by multiple arithmetic units. Each arithmetic unit processes a portion of the data using its internal memory, avoiding the need to read/write from external memory during calculation, thus maintaining high calculation speed while handling large image data volumes.
Solution Approach 2:
The patent transitions from a single arithmetic unit processing entire images to multiple arithmetic units processing segmented sub-images in parallel. This dimensional expansion from single-unit sequential processing to multi-unit parallel processing enables handling of large data volumes without external memory bottlenecks.
2Quantity of substance
If arithmetic unit is upgraded with high-capacity internal memory, then the memory capacity is improved, but the cost increases sharply
Solution Approach 1:
Instead of upgrading a single arithmetic unit with expensive high-capacity memory, the system segments the processing task across multiple arithmetic units with standard internal memory capacity. This approach achieves the same effective memory capacity for large image processing at much lower cost by using parallel processing of segmented data.
Solution Approach 2:
Multiple arithmetic units with standard internal memory are used in parallel, effectively copying the processing capability across multiple units. This allows the system to handle data volumes equivalent to high-capacity memory without actually implementing high-capacity memory in each unit, thereby reducing hardware cost.
3Quantity of substance
If external memory is used for caching results, then the data storage capability is improved, but the reading and writing speed deteriorates
Solution Approach 1:
By segmenting the image data and processing it in parallel across multiple arithmetic units, each unit operates on smaller data subsets that fit within internal memory. This eliminates the need for frequent read/write operations to external memory, maintaining high data access speed while achieving effective storage capability through parallel processing.
Solution Approach 2:
Multiple arithmetic units perform convolution operations continuously and simultaneously on different sub-images, eliminating the idle time that would occur during external memory read/write operations. This continuous parallel computation maintains high processing speed without relying on external memory bandwidth.
4Productivity
If arithmetic units are replaced with different models to handle larger data, then the data processing capability is improved, but the adaptability deteriorates
Solution Approach 1:
The patent uses multiple arithmetic units of the same model, each capable of universally processing image data through standard convolution operations. This universal design allows the system to scale processing capability by adding more units of the same type rather than requiring specialized different models, thereby maintaining high adaptability while improving data processing capability.
Solution Approach 2:
By segmenting the processing task rather than upgrading individual unit capabilities, the system maintains arithmetic unit adaptability. Each unit continues to handle standard image processing tasks, and the segmented approach allows flexible scaling by adding identical units without requiring changes to the arithmetic unit models themselves.
Data Source
AI summary
The image processing apparatus comprises at least a first arithmetic unit and a second arithmetic unit. The first arithmetic unit and the second arithmetic unit are cascaded by means of a serial transceiver, and are configured to execute the image processing method in parallel. The image processing method comprises: acquiring sub-images obtained by segmenting an original image by an external processor, and using the sub-images as current-level result images; extracting current-level image elements in the current-level result images according to a specified convolution kernel and the segmentation mode in which the sub-images are obtained; sending the current-level image elements to a front-level arithmetic unit, and receiving a back-level image elements sent by a back-level arithmetic unit; synthesizing the current-level result images and the back-level image elements into current-level images to be processed; and performing convolution operation on said current-level images to obtain the current-level result images.