Cascaded Clock Gating for Glitch-Resistant Multiphase Clocks
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Solution Overview
Problem
Clock gating with multiphase clocks faces challenges in ensuring proper timing of the clock gating control signal, leading to potential mistimed or glitched signals due to parallel routing requirements.
Innovation Solution
A cascaded clock gating control signal approach using B-latches and AND gates, where each B-latch is enabled by a corresponding clock signal, allowing the control signal to cascade through the logic to gate clock signals without parallel routing, ensuring proper timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If parallel routing is used to control multiple clock signals, then clock gating can be implemented for each phase, but timing accuracy deteriorates leading to mistimed or glitched signals
Solution Approach 1:
The patent segments the clock gating control into sequential stages corresponding to each clock phase. Instead of using a single parallel control signal, the control is divided into multiple sequential control signals, each generated for a specific clock phase. This segmentation allows each phase to be controlled independently and sequentially, eliminating the timing conflicts that arise from parallel routing while maintaining the ability to gate multiple clock phases.
2Ease of operation
If clock gating control signals are routed in parallel to separate logic for each clock signal, then clock gating functionality is achieved, but timing precision deteriorates
Solution Approach 1:
The patent applies preliminary action by generating control signals sequentially before each clock phase occurs. Each control signal is prepared in advance for its specific clock phase, ensuring that the control logic is ready and synchronized before the clock edge arrives. This preliminary preparation eliminates timing precision issues by ensuring that control signals are generated with the correct timing relationship to their corresponding clock phases, rather than relying on parallel routing that cannot guarantee precise timing.
Data Source
AI summary
A clock circuit for clock gating using a cascaded clock gating control signal, including: a first B-latch accepting, as input, a clock gating control signal and enabled by a first clock signal; a second B-latch accepting, as input, an output from the first B-latch and enabled by a second clock signal; and a first logic outputting, based on the first B-latch, a first gated clock signal; and a second logic outputting, based on the second B-latch, a second gated clock signal.