Cascaded Clock Adjustment Circuits for Jitter-Reduced Clock Multiplication
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Solution Overview
Problem
Semiconductor devices, such as memory devices, face challenges in generating clock signals with varying frequencies while minimizing jitter, which affects their operational performance due to limited physical space for clock generating circuitry and increasing complexity.
Innovation Solution
The implementation of cascaded clock adjustment circuits that utilize a reduced frequency input clock to generate full frequency clock signals, ensuring all clock signals originate from the same initial edge, thereby eliminating intra-burst jitter through clock multiplication, using edge detector circuits and duty cycle correctors to achieve this.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple clock signals with different frequencies are generated using separate clock generating circuitry, then operational versatility is improved, but device area increases and jitter increases
Solution Approach 1:
A single clock generating circuit is designed to produce multiple clock signals with different frequencies by utilizing different combinations of buffer circuits and delay elements. The same basic circuit structure serves multiple functions by generating CLK, CLK/2, CLK/4, and other divided clock signals, eliminating the need for separate dedicated circuitry for each frequency.
Solution Approach 2:
The clock generating circuit is segmented into modular components including buffer circuits, delay elements, and selection logic that can be independently configured. This segmentation allows the same circuit blocks to be reused in different configurations to generate various clock frequencies, reducing overall circuit area while maintaining versatility.
2Adaptability or versatility
If multiple clock signals with different frequencies are generated using separate clock generating circuitry, then operational versatility is improved, but jitter increases
Solution Approach 1:
Multiple clock signals are generated from a single common clock source within the same circuit architecture. By merging the generation path and using shared reference clocks, the patent ensures that all clock signals maintain consistent timing relationships and exhibit uniform jitter characteristics, preventing the jitter divergence that would occur with separate independent clock generators.
Solution Approach 2:
The clock generating circuit uses homogeneous delay elements and buffer structures throughout, ensuring that all generated clock signals have matching jitter profiles. The consistent use of the same circuit topology and timing elements across different frequency outputs guarantees uniform temporal characteristics and predictable jitter behavior.
3Productivity
If device size is reduced to fit more operations, then integration density is improved, but space for clock generating circuitry decreases
Solution Approach 1:
The clock generating circuit is designed as a universal multi-functional unit that can produce multiple clock frequencies (CLK, CLK/2, CLK/4, etc.) from a single structure. This eliminates the need for separate dedicated clock generators for each frequency, dramatically reducing the total area required for clock circuitry while enabling diverse operational modes.
Solution Approach 2:
The circuit employs a nested hierarchy where divided clock signals are generated by cascading delay elements and buffer stages. Each stage builds upon the previous one, with CLK/2 generated from CLK, CLK/4 from CLK/2, and so on. This nested structure maximizes area efficiency by reusing the same physical circuit blocks across multiple frequency generations.
Data Source
AI summary
A device includes a clock input circuit that when in operation receives a clock signal and transmits an internal clock signal based on the clock signal. The device also includes an internal clock generator coupled to the clock input circuit to receive the internal clock signal, wherein the internal clock generator comprises clock adjustment circuitry that when in operation generates a phase controlled internal clock signal having subsequent clock edges based upon a single clock edge of the internal clock signal, wherein the phase controlled internal clock signal comprises a first frequency as a multiple of a second frequency of the internal clock signal.