Cascaded Clock Ring Bus FIFO Synchronization
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Solution Overview
Problem
In cascaded clock ring networks, the phase difference between the first and last processing nodes' clock signals is unknown due to environmental factors, leading to unpredictable setup and hold times for flip-flops, which existing solutions like PLLs and DLLs fail to address effectively, especially in large die areas where clock tree balancing is difficult and power consumption is high.
Innovation Solution
A cascaded clock ring network with a FIFO memory structure that synchronizes data transfer by using a source clock signal to write and read data values, ensuring that end data values are stored and retrieved within a valid data window period, and includes a synchronizing circuit to manage phase drift and jitter, with control circuitry for periodic delay measurement and re-synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a balanced clock tree is used to provide clock signals to all processing nodes, then clock skew is minimized and operating frequency is maximized, but device complexity and power consumption increase significantly
Solution Approach 1:
The patent segments the clock distribution into two parts: a balanced clock tree for local nodes (minimizing skew) and a cascaded ring for long-distance propagation. This divides the clocking function so that each segment can be optimized independently, reducing overall complexity while maintaining high frequency operation.
Solution Approach 2:
The patent introduces a FIFO buffer as an intermediary between the cascaded clock ring and the flip-flop. This mediator absorbs the phase uncertainty and timing skew introduced by the ring topology, allowing the system to achieve high operating frequencies without requiring a complex balanced clock tree throughout the entire system.
2Device complexity
If a cascaded clock ring topology is used to reduce clock tree complexity, then device complexity and power consumption are reduced, but phase difference between clock signals becomes unknown and setup/hold times become unpredictable
Solution Approach 1:
The FIFO buffer serves as a timing mediator that decouples the unknown phase relationship in the cascaded ring from the flip-flop timing requirements. It provides a valid data window that ensures reliable data capture despite phase drift, making setup and hold times predictable again.
Solution Approach 2:
The system performs preliminary synchronization by using the FIFO to store and align data before it reaches the flip-flop. This preliminary action of buffering and timing alignment ensures that data is captured at the correct moment regardless of the cascaded ring's phase variations.
3Reliability
If PLL or DLL circuits are used to synchronize clock phases, then phase alignment is achieved, but device complexity and power consumption increase
Solution Approach 1:
The patent replaces complex, power-intensive PLL/DLL circuits with a simple FIFO buffer that uses standard digital logic. This disposable-like approach uses a straightforward buffering mechanism instead of sophisticated analog phase-locked loops, achieving synchronization with much lower complexity and power consumption.
Solution Approach 2:
The patent substitutes the mechanical/analog phase-locking mechanisms of PLLs and DLLs with a digital FIFO buffering approach. This replacement uses digital storage and timing logic instead of analog voltage-controlled oscillators and phase detectors, significantly reducing complexity and power requirements while maintaining phase synchronization.
4Reliability
If FIFO buffer is used to synchronize data transfer, then data transfer reliability is improved, but latency increases
Solution Approach 1:
The patent uses a partial FIFO buffer approach where only the necessary number of buffer stages are implemented to handle the maximum expected phase drift. This partial action provides sufficient synchronization without the excessive latency that would result from using a large buffer depth, optimizing the trade-off between reliability and speed.
Data Source
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AI summary
A cascaded clock ring network includes a clock path that transmits a source clock through series-connected processing nodes, from a first processing node to a last processing node. A data path transmits data through the processing nodes in response to the transmitted source clock, from the first processing node to the last processing node. The last processing node provides the transmitted source clock as an end clock signal, and provides the transmitted data as end data values. The end data values are written into a FIFO memory in response to the end clock signal. The end data values are subsequently read from the FIFO memory using the source clock signal, and are provided to the first processing node. A synchronizing circuit ensures that a plurality of end data values are initially written into the FIFO memory before an end data value is read from the FIFO memory.