Cascaded Programmable Frequency Divider With Reduced Duty-Cycle Variation
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Solution Overview
Problem
Existing programmable frequency dividers experience significant duty-cycle variations when adjusting divide ratios, which can lead to increased phase-noise and jitter in output signals, particularly when fractional divide ratios are required.
Innovation Solution
A programmable frequency divider is designed using a cascade of frequency-dividing units that can operate as either a divide-by-2 or divide-by-3 unit, with mode control signals determining the division factor in each cycle, allowing for minimal duty-cycle variations across a range of divide ratios by ensuring the highest unit's mode control signal is always active and the lowest unit's signal is used to generate the final divided clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a programmable frequency divider uses different integer divide ratios over multiple iterations to achieve fractional divide ratios, then the desired fractional divide ratio is achieved, but the duty cycle of the output signal varies significantly
Solution Approach 1:
The patent implements dynamic control of the frequency divider by using a feedback mechanism that continuously adjusts the divide ratio based on the phase difference between the reference signal and feedback signal. This dynamic adjustment allows the system to maintain a stable duty cycle while achieving fractional divide ratios, as the divider ratio is modified in real-time rather than using fixed integer values over multiple iterations
Solution Approach 2:
The patent employs a phase-locked loop (PLL) architecture with feedback from the divided output signal to the phase detector. The phase detector compares the phase of the reference signal with the feedback signal and generates control signals that adjust the divide ratio dynamically. This feedback mechanism ensures that the duty cycle remains stable while achieving the desired fractional divide ratio, eliminating the need for multiple iterations with different integer divide ratios
2Adaptability or versatility
If the frequency divider adjusts divide ratios to provide programmable output frequencies, then the desired output frequency is achieved, but phase-noise and jitter increase in the output signal
Solution Approach 1:
The feedback mechanism in the PLL architecture continuously monitors the phase difference between the reference and feedback signals, allowing for real-time correction of phase deviations. This continuous phase correction minimizes phase-noise and jitter in the output signal while maintaining the ability to program different output frequencies through dynamic adjustment of the divide ratio
Solution Approach 2:
The patent replaces traditional mechanical or fixed digital frequency division methods with an electronic feedback-based system. The phase detector and charge pump circuitry provide continuous electronic adjustment of the divide ratio, which reduces the quantization effects and mechanical instability associated with fixed integer divide ratios, thereby reducing phase-noise and jitter
3Adaptability or versatility
If a cascade of frequency-dividing units is used to achieve a wide range of divide ratios, then the range of programmable ratios is expanded, but the hardware complexity increases
Solution Approach 1:
The patent implements a universal frequency-dividing unit that can operate with different divide ratios through dynamic control signals. Instead of requiring separate hardware circuits for each divide ratio, the same frequency-dividing unit can be reconfigured to achieve various divide ratios by adjusting the control inputs to the phase detector and counter. This multi-functionality reduces hardware complexity while maintaining a wide programmable range
Solution Approach 2:
The system uses dynamic control of the divide ratio through a programmable counter and control logic that adjusts the division factor in real-time. This dynamic approach allows a single frequency-dividing unit to replace multiple fixed divide-by-N circuits, achieving a wide range of divide ratios without proportionally increasing hardware complexity. The control logic dynamically selects the appropriate divide ratio based on the desired output frequency
Data Source
AI summary
A programmable frequency divider includes a cascade of frequency-dividing units, each capable of dividing by a first or a second factor. Each unit receives an input clock and generates a divided output clock. Each unit receives a mode control signal that specifies when to divide its input clock by the second factor if a control input allows it, otherwise dividing the input clock by the first factor. The frequency divider is designed to support a range of divide ratios that requires one or more of the units to be non-operative or unused in some intervals. The final divided clock is generated using the mode control signal of the lowest unit in the cascade and the mode control signal of the highest unit that is never set to be non-operative or unused in supporting the range. As a result, duty-cycle variations of the final divided clock are minimized.