Cascaded 1D Downscaler Layout for Large-Factor Image Reduction
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Solution Overview
Problem
Existing hardware scalers are not particularly efficient in downsampling high-resolution image data, leading to significant computational and memory requirements, especially when reducing images by large factors like 20 for input into convolutional neural networks (CNNs).
Innovation Solution
A hardware downscaling module comprising a cascaded series of fixed factor downscalers, with each downscaler applying a 2:1 downsampling factor, followed by a variable downscaler to achieve the desired overall downsampling factor, and optionally incorporating bypasses to allow for a range of downsampling factors, implemented using a combination of one-dimensional downscalers in series in both dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single hardware scaler is used to downsample high-resolution image data by large factors (e.g., 20x), then the downsampling task can be completed, but the computational and memory requirements become excessively high
Solution Approach 1:
The patent divides the single complex downsampling operation into multiple simpler stages. Instead of using one hardware scaler to perform large-factor downsampling in a single step, the system employs a series of downscalers that each perform smaller downsampling operations (e.g., 2x, 3x, 5x factors). This segmentation reduces the memory buffer requirements at each stage compared to a single large-factor scaler, while achieving the same overall downsampling efficiency.
2Productivity
If a single hardware scaler is used to downsample high-resolution image data by large factors (e.g., 20x), then the downsampling task can be completed, but the computational complexity and power consumption increase significantly
Solution Approach 1:
The patent segments the downsampling operation into multiple stages, each handled by a dedicated downscaler performing a specific downsampling factor. This approach reduces the computational complexity at each stage compared to a single scaler handling the entire 20x reduction. Each downscaler processes a portion of the work, reducing the overall power consumption while maintaining the required downsampling efficiency.
3Quantity of substance
If a series of fixed factor downscalers are used to exponentially increase the downsampling factor, then memory requirements are reduced, but precise control over the final downsampling factor becomes difficult
Solution Approach 1:
The patent incorporates a variable downscaler in the final stage of the downsampling pipeline. While the earlier stages use fixed-factor downscalers (providing exponential scaling with reduced memory), the variable downscaler allows dynamic adjustment of the downsampling factor to achieve precise control over the final output resolution. This combination maintains the memory efficiency of fixed-factor stages while adding the adaptability needed for precise downsampling control.
4Productivity
If hardware scalers are designed to handle large downsampling factors, then they can process high-resolution images, but the device complexity increases
Solution Approach 1:
The patent segments the complex hardware scaling function into multiple simpler downscaler modules. Instead of designing one complex hardware scaler capable of handling all downsampling factors, the system uses several downscalers with simpler, dedicated functions (each handling specific downsampling factors). This segmentation reduces the complexity of individual hardware components while maintaining the overall capability to process high-resolution images at various downsampling levels.
Data Source
AI summary
A hardware downscaling module and downscaling methods for downscaling a two-dimensional array of values. The hardware downscaling unit comprises a first group of one-dimensional downscalers; and a second group of one-dimensional downscalers; wherein the first group of one-dimensional downscalers is arranged to receive a two-dimensional array of values and to perform downscaling in series in a first dimension; and wherein the second group of one-dimensional downscalers is arranged to receive an output from the first group of one-dimensional downscalers and to perform downscaling in series in a second dimension.