Cascaded Interpolation Filter Circuit for Low-Delay Audio DACs
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Solution Overview
Problem
Existing digital interpolation filters suffer from complexity, large register arrays, and increased delay with multiple stages, leading to design challenges and potential operational faults, especially in digital circuits used for audio DACs.
Innovation Solution
A digital interpolation filtering system with a cascaded structure, utilizing an interpolation filtering operation controller, cascaded drive modules, intermediate result cache RAM, and filter coefficient storage ROM, controlled by a master state machine, which performs multiplication and accumulation operations to achieve efficient interpolation filtering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If parallel logic structure with large register arrays is used, then filtering performance is improved, but device complexity and chip area increase
Solution Approach 1:
The interpolation filter is divided into multiple cascaded stages, where each stage performs a portion of the filtering operation. This segmentation allows the complex filtering task to be distributed across simpler modular units, reducing the complexity of individual stages while maintaining overall filtering performance through the cascaded structure.
Solution Approach 2:
The patent employs a sequential processing approach where data flows through multiple stages in a periodic manner, with each stage processing data in sequence rather than simultaneously. This periodic action through cascaded stages reduces the need for large parallel register arrays while maintaining filtering accuracy through repeated processing passes.
2Measurement precision
If multiple stages of digital circuit are increased, then filtering accuracy is improved, but delay increases
Solution Approach 1:
The patent pre-calculates and stores filter coefficients in ROM memory before the actual filtering operation. This preliminary preparation of coefficients allows the cascaded stages to operate more efficiently without waiting for coefficient computation, thereby reducing the overall delay introduced by multiple processing stages while maintaining filtering accuracy.
3Productivity
If parallel logic structure is used, then processing speed is improved, but chip area and hardware resources increase
Solution Approach 1:
The patent implements a dynamic sequential processing architecture where the processing pipeline adapts through cascaded stages. Instead of static parallel processing that requires all resources simultaneously, the dynamic sequential approach through multiple stages allows hardware resources to be reused across different time periods, reducing chip area while maintaining acceptable processing speeds through the cascaded structure.
Data Source
Figure 1
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AI summary
An interpolation filtering system implemented by a digital circuit, including an interpolation filtering operation controller, a cascaded drive module, an intermediate result cache Random Access Memory (RAM), and a filter coefficient storage Read Only Memory (ROM). The interpolation filtering operation controller includes cascaded filter operation modules and a master state machine. The intermediate result cache RAM is configured to store externally input data of the interpolation filtering system and intermediate results output by the filter operation modules. The filter coefficient storage ROM is configured to store filter coefficients required for calculation by the filter operation modules. The interpolation filtering operation controller is configured to control, under the drive of counting beats output by the cascaded drive module, the master state machine to select data of the intermediate result cache TAM or externally directly input data to be sent to the cascaded filter operation modules for accumulation operation, and to select the filter coefficients of the filter coefficient storage ROM for multiplication operation, thereby achieving the objective of interpolation filtering after the processing by the cascaded filter operation modules is performed.