Cascaded MOSFET Gate Driver Timing for Inrush Current Control
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Solution Overview
Problem
Existing power electronic systems face challenges with inrush current limitations and unequal current sharing during startup, leading to potential device failure and increased costs due to the use of standard MOSFETs or Linear FETs as disconnect switches.
Innovation Solution
A gate driver circuit with configurable turn-on and turn-off delays for multiple disconnect switches, where a first switch turns on before a second switch to manage inrush currents and prevent avalanching, using different transistor types for optimal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If standard MOSFETs are used as disconnect switches, then the system structure is simple, but inrush current is not limited during system power on
Solution Approach 1:
The disconnect switch function is segmented into two separate MOSFETs (first and second MOSFETs) that operate at different times. The first MOSFET handles inrush current limiting during startup, while the second MOSFET takes over for normal operation, thereby resolving the contradiction between simple structure and inrush current protection.
Solution Approach 2:
The first MOSFET is activated before the second MOSFET during startup to preemptively limit inrush current. This preliminary action ensures that the bulk capacitor charges through a controlled path before the main power path is established, preventing damage while maintaining structural simplicity.
2Reliability
If several MOSFETs in parallel are used as disconnect switches, then inrush current can be handled, but unequal current sharing occurs during inrush current transients
Solution Approach 1:
The first MOSFET is activated in advance during startup to exclusively handle inrush current before the second MOSFET is turned on. This preliminary activation eliminates the current sharing problem by ensuring that only one MOSFET conducts during the critical inrush transient, while still providing the capability to handle high inrush currents.
3Reliability
If Linear FETs are used to limit inrush current and ensure equal current sharing, then current control is improved, but faster turn off can lead to avalanching and device failure
Solution Approach 1:
The switching function is segmented between two MOSFETs with different gate control signals. The first MOSFET can be turned off quickly to limit inrush current, while the second MOSFET is turned off with a delayed signal, allowing its drain-source voltage to rise gradually and avoid avalanching, thus resolving the contradiction between current control and device safety.
Solution Approach 2:
The second MOSFET is turned off after a deliberate delay following the first MOSFET's turn-off signal. This preliminary timing arrangement ensures that the first MOSFET has already stopped conducting before the second MOSFET begins to turn off, preventing current redistribution that would cause avalanching while maintaining effective inrush current limiting.
4Ease of manufacture
If standard MOSFETs are selected with assumption that single MOSFET takes entire inrush current, then device selection is simplified, but cost increases due to selecting higher rated devices
Solution Approach 1:
The inrush current handling function is segmented between two MOSFETs, allowing each device to be rated for lower current than the total inrush current. This segmentation enables the use of lower-cost, lower-rated MOSFETs while still providing adequate protection, resolving the contradiction between manufacturing simplicity and cost reduction.
Data Source
Figure 1
Figure 2
Figure 3A~3B
AI summary
A gate driver circuit (116) includes at least one driver configured to generate a first gate control signal (A) for a first power disconnect switch (112) and a second gate control signal (B) for a second power disconnect switch (114) in parallel with the first power disconnect switch, and logic (118) configured to implement a delayed turn on time for the second gate control signal compared to the first gate control signal such that the first power disconnect switch turns on before the second power disconnect switch when powering up a load (108) coupled to the first and the second power disconnect switches. The gate driver circuit logic may also be configured to implement a delayed turn off time such that the first power disconnect switch turns off before the second power disconnect switch when powering down the load. Corresponding power conversion circuits, electronic systems, and methods of power disconnect switch control are also described.