Cascaded Gate Driver Circuit With Two-Switch Driving Units
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Solution Overview
Problem
Conventional integrated gate driver circuits for liquid crystal displays have complex structures and require significant manufacturing space, leading to increased costs and reduced yield due to the need for multiple thin film transistors and extensive line formation on a single substrate.
Innovation Solution
An integrated gate driver circuit design utilizing only two switching devices per driving unit, with a voltage stabilizing circuit and capacitors to simplify the structure and reduce space requirements, and employing a clock generator to manage signal input and output through cascaded driving units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional integrated gate driver circuits are formed on a single substrate with pixel matrix, then manufacturing cost is reduced, but circuit structure becomes complex and manufacturing space increases
Solution Approach 1:
The patent merges the gate driver circuit and pixel matrix onto a single substrate, integrating multiple functions into one device. This combining approach reduces the number of separate components and interconnections, thereby lowering manufacturing cost while maintaining a manageable circuit structure through shared substrate infrastructure.
Solution Approach 2:
The gate driver circuit is designed with multi-functional capabilities that allow it to serve multiple purposes within the display system. By making the driver circuit universal in its functionality, the overall system complexity is reduced as fewer specialized components are needed, achieving cost reduction without proportionally increasing structural complexity.
2Ease of manufacture
If conventional integrated gate driver circuits are formed on a single substrate with pixel matrix, then manufacturing cost is reduced, but manufacturing space increases
Solution Approach 1:
The patent employs a nested arrangement where the gate driver circuit is integrated within the same substrate as the pixel matrix, with driver circuit elements positioned in unused or marginal areas of the substrate. This nesting strategy allows both functions to coexist on one substrate without requiring proportional increases in total manufacturing space, as the driver circuit utilizes available space efficiently around the pixel array.
3Reliability
If each driving stage includes six thin film transistors, then switching functionality is achieved, but circuit structure becomes complicated and manufacturing yield decreases
Solution Approach 1:
The patent extracts and eliminates redundant transistors from the conventional six-transistor driving stage design. By carefully analyzing the essential switching functions required and removing unnecessary components, the circuit achieves the same switching functionality with fewer transistors, thereby simplifying the circuit structure and improving manufacturing yield without compromising reliability.
4Manufacturing precision
If more gate lines, data lines and pixels are formed simultaneously on one substrate, then resolution is increased, but available space for gate driver circuits decreases
Solution Approach 1:
The patent applies local quality optimization by positioning the gate driver circuit in specific regions of the substrate where space is more readily available, such as along the edges or in non-active areas. This localized placement strategy allows high-resolution pixel matrices to occupy the central high-value area while the driver circuit utilizes peripheral spaces, thereby maintaining both high resolution and adequate driver circuit space on the same substrate.
Data Source
AI summary
An integrated gate driver circuit receives a plurality of clocks and includes a plurality of driving units cascaded in series. Each driving unit is for driving a load and includes an input terminal, an output terminal, a first switch and a second switch. The first switch has a first terminal coupled to the input terminal, a second terminal coupled to a first node, and a control terminal receiving a first clock, and the first switch is turned on when the first clock is at high level. The second switch has a first terminal receiving a second clock, a second terminal coupled to the output terminal, and a control terminal coupled to the first node, wherein the second clock charges and discharges the load through the second switch when the first node is at high level; wherein the output terminal of each driving unit is coupled to the input terminal of the immediately succeeding driving unit.