Cascaded Gate Driving Module for Foldable Display Power Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional gate driving circuits for foldable display panels face issues with clock signal mismatch and unequal gate loading, leading to split-screen phenomena when the panel is folded, due to the lack of cascaded connection between gate driving circuits, resulting in increased power consumption.
Innovation Solution
A gate driving module with cascaded shift register sub-circuitries and a control circuit that applies voltage signals to clock signal lines to manage gate driving signals, allowing for efficient control of transistors in different display sub-regions, especially when the panel is folded, thereby reducing power consumption and preventing image display in non-viewable areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If at least two gate driving circuits are provided for at least two display sub-regions when the display panel is folded, then power consumption is reduced by turning off shift register units in non-display regions, but clock signal mismatch and gate loading differences occur between the gate driving circuits, leading to split-screen phenomena
Solution Approach 1:
The patent merges multiple gate driving circuits into a single gate driving circuit that can control the entire display panel. This unified circuit design eliminates the clock signal mismatch and gate loading differences that occur between separate circuits, thereby preventing split-screen phenomena while maintaining the ability to reduce power consumption by controlling shift register units in non-display regions.
Solution Approach 2:
The gate driving circuit is designed with multi-functionality to handle both full-screen and folded display modes. It can dynamically adjust its operation to drive different display sub-regions based on the panel state, providing universal control capability that eliminates the need for separate dedicated circuits for each sub-region while maintaining image quality and power efficiency.
2Adaptability or versatility
If at least two gate driving circuits are provided for different display sub-regions, then each sub-region can be controlled independently, but the gate driving circuits are not connected in cascaded manner causing clock signal mismatch
Solution Approach 1:
The patent combines multiple gate driving circuits into one unified circuit that maintains independent control capability for different display sub-regions. This unified structure ensures clock signal synchronization across all regions by eliminating the separation that causes mismatch, while still allowing selective activation of shift register units based on display mode.
Solution Approach 2:
The gate driving circuit employs dynamic control mechanisms to adapt its operation based on the display mode (full-screen or folded). It can dynamically enable or disable specific shift register units and adjust scanning patterns accordingly, providing independent control for different sub-regions when needed while maintaining clock signal synchronization through its unified dynamic architecture.
Data Source
AI summary
The present disclosure provides a gate driving module, including a gate driving circuit and a control circuit. The gate driving circuit includes a first shift register sub-circuitry and a second shift register sub-circuitry connected to each other in a cascaded manner. A first shift register unit is connected to a corresponding gate line at a first display sub-region. A second shift register unit is connected to a clock signal line and a corresponding gate line at a second display sub-region, and configured to generate a gate driving signal in accordance with a voltage signal on the clock signal line and output the gate driving signal to the gate line. The control circuit is configured to, when a display panel is in a non-planar state and the second shift register unit is performing a gate driving scanning operation, apply a first voltage signal to the clock signal line, so as to enable the second shift register unit to output a signal for turning off a transistor corresponding to the gate line.