Cascaded GOA Circuit for Display Panel Border Width Reduction
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Solution Overview
Problem
Conventional 2G1D mode in eight-domain displays increases the number of chip on films (COF) and fanouts in the gate driver on array (GOA) circuit, leading to higher manufacturing costs and a wider border, while also exacerbating the color difference and color washout phenomena, especially when viewed from the side.
Innovation Solution
A cascaded GOA circuit design that includes a cascade control unit, cascade signal generation unit, first and second scan drive units, and pull-down units to generate and control drive signals for both main and sub pixels, allowing for simultaneous output of main and sub pixel scan signals with different voltage waveforms, thereby improving color difference and washout issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the 2G1D mode is adopted in the conventional pixel design, then the gate drive voltages of main pixel and sub pixel can be independently controlled to improve color difference and color washout, but the number of chip on films (COF) and fanouts in the GOA circuit increases
Solution Approach 1:
The patent merges the gate drive circuits for main pixel and sub pixel into a single shared circuit structure. The GOA circuit generates scan signals that are simultaneously applied to both main pixel and sub pixel, eliminating the need for separate gate drive circuits. This merging approach reduces the number of COF and fanouts while still enabling independent brightness control through different scan signal timing and voltage levels for main and sub pixels.
Solution Approach 2:
The patent implements a universal gate drive circuit that serves multiple functions: it generates scan signals for both main pixel and sub pixel, controls their respective brightness independently, and maintains compatibility with the existing GOA architecture. The single gate drive circuit is designed to handle multiple pixel types (main and sub pixels) with different brightness requirements, achieving multi-functionality without increasing circuit complexity.
2Object-affected harmful factors
If the 2G1D mode is adopted in the conventional pixel design, then the gate drive voltages of main pixel and sub pixel can be independently controlled, but the manufacturing cost increases
Solution Approach 1:
By merging the gate drive circuits into a single shared structure, the patent reduces the number of COF components and fanout connections required. This consolidation directly lowers manufacturing costs by reducing material usage and assembly complexity, while the circuit maintains the capability to independently control main and sub pixel brightness through optimized scan signal generation.
3Object-affected harmful factors
If the 2G1D mode is adopted in the conventional pixel design, then the gate drive voltages of main pixel and sub pixel can be independently controlled, but the border width increases
Solution Approach 1:
The patent merges the gate drive circuits for main and sub pixels into a compact shared structure, which reduces the horizontal space required for the GOA circuit. This merging eliminates the need for separate circuit blocks that would increase border width, while still providing independent brightness control through optimized signal timing and voltage levels for different pixel types.
Data Source
AI summary
A GOA circuit is provided and includes a plurality of GOA sub circuits which are cascaded. An Nth GOA sub circuit of the GOA sub circuits includes: a cascade control unit configured to generate a first drive signal according to an (N−3)th scan signal and an (N−3)th cascade signal; a cascade signal generation unit connected to the cascade control unit; a first scan drive unit connected to the cascade control unit and a first low voltage level signal; and a second scan drive unit connected to the cascade control unit and the first low voltage level signal.