Cascaded GOA Display Panel for Narrow-Frame Buffer Layout

The patent changes the spatial arrangement from vertical stacking (one dimension) to horizontal distribution along the first direction (another dimension). The first and second buffer parts are disposed at different positions along the first direction, which is parallel to the scan lines, rather than stacking them vertically. This dimensional change allows both buffer parts to be accommodated without increasing the vertical frame size, thus resolving the contradiction between transistor performance and frame size.

The gate driving circuit is segmented into multiple GOA units, each with its own buffer parts. The first buffer part outputs a first gate driving signal and the second buffer part outputs a second gate driving signal. This segmentation allows the buffer parts to be distributed along the first direction, reducing the need for vertical stacking and thereby reducing the overall frame size while maintaining the required transistor performance for each buffer part.

Instead of reducing the vertical size of buffer parts, the patent extends the buffer parts along the first direction (horizontal dimension parallel to scan lines). This allows the buffer parts to maintain sufficient area for good transistor performance while being arranged in a way that does not increase the vertical frame size, thus achieving narrow frame design without sacrificing transistor performance.

The patent employs asymmetric arrangement where the first buffer part and second buffer part are positioned at different locations along the first direction, with the first buffer part closer to the display area than the second buffer part. This asymmetric distribution optimizes the use of available space, allowing each buffer part to have adequate size for transistor performance while fitting within the narrow frame constraints.