Cascaded GOA Panel Layout for Narrow OLED Display Frames
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Solution Overview
Problem
Existing OLED display panels face the issue of excessively large frames due to the need for two buffer parts in the CMOS GOA circuit, which are typically located close to the display area, necessitating a wider frame design that contradicts the narrow frame design trend.
Innovation Solution
The display panel incorporates a gate driving circuit with N cascaded GOA units disposed along a first direction, featuring distinct first and second output modules with different lengths and orientations, allowing for sufficient transistor performance while minimizing frame size, and utilizing a combination of low temperature polysilicon and metal oxide semiconductors to optimize transistor characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two buffer parts are disposed close to the display area in the CMOS GOA circuit, then transistor performance is ensured, but the frame size becomes excessively large
Solution Approach 1:
The patent repositions the buffer parts from a vertical arrangement (close to display area) to a horizontal arrangement (close to frame). Specifically, the first buffer part is disposed close to the frame rather than close to the display area, and the second buffer part is disposed on the other side of the signal generation part. This dimensional change in layout allows sufficient transistor performance while minimizing frame size.
2Reliability
If the buffer part size is increased in the horizontal direction to ensure transistor performance, then transistor reliability is improved, but the frame area requires wider reservation
Solution Approach 1:
The patent employs asymmetric positioning of the two buffer parts relative to the signal generation part. The first buffer part is disposed close to the frame while the second buffer part is disposed on the other side of the signal generation part. This asymmetric arrangement optimizes space utilization and allows transistor performance requirements to be met without proportionally increasing the overall frame area.
Solution Approach 2:
The patent changes the spatial arrangement from vertical stacking to horizontal distribution, positioning buffer parts at different locations along the horizontal axis rather than stacking them vertically near the display area. This dimensional reconfiguration reduces the vertical space requirement while maintaining transistor performance.
3Reliability
If the gate driving circuit is designed with sufficient area for two buffer parts, then signal generation performance is ensured, but the narrow frame design objective is compromised
Solution Approach 1:
The patent repositions the buffer parts from a vertical arrangement (close to display area) to a horizontal arrangement (close to frame). Specifically, the first buffer part is disposed close to the frame rather than close to the display area, and the second buffer part is disposed on the other side of the signal generation part. This dimensional change in layout allows sufficient transistor performance while minimizing frame size.
Solution Approach 2:
The patent divides the buffer parts into two separate locations: one close to the frame and another on the opposite side of the signal generation part. This segmentation allows each buffer part to be optimally positioned for its function while distributing the space requirements across different regions, thereby maintaining signal generation performance without concentrating all buffer requirements in one location that would increase frame width.
Data Source
AI summary
A display panel includes N GOA units disposed along a first direction. Each GOA unit includes a first output module, a signal generation module, and a second output module disposed along a second direction. The first output module is configured to output a first gate driving signal, and the second output module is configured to output a second gate driving signal. The first gate driving signal is different from the second gate driving signal, and a length of the first output module is different from a length of the second output module.