Cascaded Image Processing Circuits with Flow Control
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Solution Overview
Problem
As the number of pixels and frame rate in image capturing devices increase, existing image processing circuits struggle to handle the resulting data, leading to signal integrity issues and high costs when using multiple circuits in parallel configurations.
Innovation Solution
An image processing apparatus is designed with multiple image processing circuits connected in series, incorporating a mechanism for flow control that separates and processes data between stages, preventing data loss by controlling data transmission based on threshold values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple image processing circuits are connected in parallel to handle increased data amounts, then processing capability is improved, but signal integrity deteriorates due to wire branching
Solution Approach 1:
Instead of connecting image processing circuits in parallel (conventional approach), the patent connects them in series. This inverts the traditional architecture, allowing high-speed data transfer without wire branching while maintaining signal integrity. The first circuit processes data from the image capturing unit, then passes it to the second circuit, eliminating the need for parallel wire branching.
2Reliability
If dedicated relay devices or terminals are provided for high-speed data transfer among multiple circuits, then signal integrity is maintained, but cost increases
Solution Approach 1:
The image processing circuits perform their own data transfer functions without requiring dedicated relay devices. The first image processing circuit includes a transmission unit that directly transmits processed data to the second circuit, and the second circuit includes a reception unit that receives data. This self-service approach eliminates the need for expensive external relay devices while maintaining reliable data transfer.
3Speed
If data is transmitted between image processing circuits without flow control, then processing speed is maintained, but data loss occurs when buffer capacity is exceeded
Solution Approach 1:
The patent implements flow control through feedback mechanisms. The second image processing circuit includes a detection unit that detects when the buffer is full and generates a control signal to stop data transmission from the first circuit. This feedback loop prevents buffer overflow and data loss while maintaining high-speed processing. The transmission unit in the first circuit responds to stop signals by pausing data transmission, ensuring reliable data transfer.
Data Source
AI summary
Image data output from an image capturing unit is input to an image processing circuit, and the image processing circuit is connected in cascade to another image processing circuit. With the image processing circuit, a portion of the image data for which processing is shared is processed by the image processing circuit, the processed image data is multiplexed by a multiplexing unit with another portion of the image data to be processed by the other image processing circuit, and is transmitted to the other image processing circuit by an output IF unit. The other image processing circuit processes its share of the image data and displays it along with the processed image data received from an image processing unit.