Cascaded Interrupt Controller Architecture for Low Latency
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Solution Overview
Problem
In multi-processor systems and highly integrated system-on-chip (SoC) architectures, existing interrupt handling mechanisms face high interrupt latency and inflexibility due to limitations in the number of interrupt requests that can be served, leading to unnecessary overhead in passing interrupt vectors and lack of flexibility in software-based interrupt vector generation.
Innovation Solution
A cascaded interrupt controller architecture that transmits only the interrupt priority and source index signals between controllers and the processing unit, allowing for scalable and flexible interrupt handling with reduced overhead, enabling software-based interrupt vector generation and efficient identification of interrupt service routines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If vectorized interrupt controllers with look-up tables are used to reduce interrupt latency, then interrupt latency is reduced, but the number of interrupt requests that can be handled increases
Solution Approach 1:
The system divides the interrupt handling function into multiple hierarchical levels: first interrupt controllers handle local interrupt requests, second interrupt controllers handle interrupts from first controllers, and the processing unit handles highest priority interrupts. This segmentation allows each component to manage a subset of interrupt requests, reducing the burden on any single component while maintaining low latency through hierarchical prioritization.
Solution Approach 2:
The patent introduces a hierarchical dimension to interrupt handling by adding multiple levels of interrupt controllers between the interrupt sources and the processing unit. Each level manages interrupts from the level below, creating a layered architecture that scales the number of handleable interrupt requests without increasing latency for high-priority interrupts.
2Device complexity
If cascaded interrupt controllers are used to handle more interrupt requests, then the number of interrupt requests handled increases, but overhead in passing interrupt vectors increases
Solution Approach 1:
The patent extracts only the essential information needed for interrupt handling - the interrupt priority level and source identification - from the full interrupt vector. By removing unnecessary vector data and passing only critical control information through the cascaded controllers, the system reduces communication overhead while maintaining the ability to handle numerous interrupt requests efficiently.
Solution Approach 2:
The intermediate interrupt controllers act as mediators that translate and forward only the necessary interrupt control signals between different hierarchical levels. These intermediaries filter out redundant information and pass only the essential priority and source identification data, reducing the overhead of information transmission across multiple controller levels.
3Device complexity
If traditional interrupt handling mechanisms are used, then the number of interrupt requests served is limited, but flexibility in software-based interrupt vector generation is reduced
Solution Approach 1:
The patent implements dynamic interrupt handling where the processing unit can programmatically determine which interrupt service routine to execute based on the interrupt priority and source identification information received from the cascaded controllers. This dynamic approach allows software-based flexibility in interrupt vector generation while maintaining the ability to handle a large number of interrupt requests through the hierarchical controller architecture.
Data Source
AI summary
A data processing system includes a first interrupt controller with an interrupt source interface, an interrupt controller interface, a prioritizer, and an interrupt controller output. The data processing system further includes a processing unit providing an interrupt controller interface. Interrupt requests generated by a first plurality of interrupt sources, a second selected interrupt request, a second priority signal, and a second interrupt source index signal generated by a second interrupt controller are received by the first interrupt controller. From the plurality of interrupt requests and the second selected interrupt request, a first single interrupt request is selected and transmitted to the processing unit along with a first priority signal, and a first index signal. The processing unit initiates an appropriate interrupt service routine on the basis of said first index signal.