Cascaded Phase Interpolator Topology for Low-Power PAM Sampling
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Solution Overview
Problem
High-speed multilevel pulse amplitude modulation (PAM) receivers face inefficiencies in power, area, and cost due to the use of power-hungry phase-interpolator (PI)-based samplers that sample over the entire 360 degrees of phase, making it complex and expensive to adjust optimized sampling phases for each level.
Innovation Solution
A cascaded phase interpolator topology is employed, using fewer global PIs that sample over the entire 360 degrees, and smaller local PIs that add a fixed phase shift to generate final-adjusted phases for sampling, reducing the need for full-scale PI samplers and optimizing power and area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If full-scale phase-interpolator (PI)-based samplers are used to sample over the entire 360 degrees of phase, then the sampling coverage is complete, but the power consumption and area increase significantly
Solution Approach 1:
The patent divides the full 360-degree phase sampling into multiple segments, each handled by a separate sampler operating at a quarter of the data rate. By using quadrature-rate clocking with four phase-shifted clocks (0°, 90°, 180°, 270°), each sampler only needs to cover a 90-degree phase range instead of the full 360 degrees, significantly reducing power consumption and area while maintaining complete sampling coverage through the combination of all samplers.
2Measurement precision
If each sampling level uses a different optimized sampling phase, then the sampling precision is improved, but the device complexity increases
Solution Approach 1:
The patent implements a universal phase adjustment mechanism that can be applied to all sampling levels through the same quadrature-rate sampling architecture. Instead of designing separate complex phase adjustment circuits for each level, the system uses a common set of four phase-shifted clocks that can be selectively applied to different sampling levels, simplifying the overall device complexity while allowing each level to achieve its optimized sampling phase.
3Adaptability or versatility
If power-hungry phase-interpolator (PI)-based samplers are used for each level, then the sampling capability is comprehensive, but the area and cost increase
Solution Approach 1:
The patent segments the sampling function across multiple samplers operating at reduced clock rates. Instead of using one or more full-scale PIs that consume significant area, the system uses multiple simpler samplers that each operate at quarter-rate with 90-degree phase coverage. The combined area of these smaller samplers is significantly less than that of equivalent full-scale PIs, while maintaining comprehensive sampling capability through the quadrature-rate architecture.
Data Source
AI summary
A receiver includes a multi-phase clock generator to generate phases of a clock signal and a global phase interpolator (PI) circuit coupled to the multi-phase clock generator and to clock and data recovery (CDR) circuitry. The global PI circuit generates initial-adjusted phases from the phases of the clock signal based on a control signal received from the CDR circuitry. A first local PI receives the initial-adjusted phases of the clock signal and applies a first fixed phase shift to the initial-adjusted phases to generate first final-adjusted phases of the clock signal that are useable to sample a first level of multiple levels of a pulse-amplitude-modulated (PAM) data stream.