Cascaded Bipolar Phase Shifter With Low-Distortion Delay Stages
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Solution Overview
Problem
Conventional phase shifters suffer from high signal distortion and increased minimum delay due to the attenuation of high-frequency components and shape changes in the input signal, leading to unwanted distortion when superimposing signals with different shapes and amplitudes.
Innovation Solution
A phase shifter design utilizing cascaded delay stages with bipolar transistors, where the second differential pairs contribute to the output current, allowing for adjustable phase shift without the need for bulky level shifters or RC filters, operating in current mode to reduce distortion and minimize delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a low pass filter or transmission line is used to delay the input signal, then the phase shift range is extended, but the high frequency components are attenuated and the signal shape is changed, resulting in increased distortion
Solution Approach 1:
The phase shifter is divided into multiple delay stages (first delay stage, second delay stage, third delay stage), each contributing a portion of the total phase shift. This segmentation allows the system to achieve a wide phase shift range (0° to 360°) without requiring each individual stage to introduce large delays that would necessitate heavy filtering.
Solution Approach 2:
The outputs of multiple delay stages are combined through a common load stage to produce the final output signal. This merging approach allows the superposition of multiple delayed versions of the input signal, achieving continuous phase shift adjustment without the need for bulky RC filters or level shifters that would distort the signal.
2Object-generated harmful factors
If RC filters are used to reduce signal distortion, then the signal quality is improved, but the minimum delay time is increased
Solution Approach 1:
The invention extracts and eliminates the need for RC filters and level shifters from the phase shifter architecture. By operating in current mode and using a common load stage to combine signals, the design achieves low distortion without introducing the additional delay that would result from filtering.
3Adaptability or versatility
If conventional phase shifter circuits with level shifters and filters are used, then the phase shift range is achieved, but the device complexity and power consumption are increased
Solution Approach 1:
The common load stage automatically combines the outputs of the delay stages through current superposition, eliminating the need for external filtering and level shifting circuits. This self-service approach reduces device complexity and power consumption while maintaining the desired phase shift range.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves lower signal distortion and reduced minimum delay time with high bandwidth, eliminating the need for additional filtering and power-consuming level shifters, while enabling precise phase shift adjustment over a broader range.
Implementation Method 1
The basic idea of a phase-shifter consists in superimposing a signal with its delayed (shifted in phase) counterpart. A conventional solution capable of a π/2 phase-shifting range... A setting V C = 0 will create an output signal superimposed by both the not delayed input V A and the delayed signal V B.
Implementation Method 2
The basic idea of a phase-shifter consists in superimposing a signal with its delayed (shifted in phase) counterpart.
Data Source
Figure 1~2
Figure 3
Figure 4A
AI summary
The present invention relates to a phase shifter, which includes at least two cascaded delay stages (1, 2) each including a first differential pair of bipolar transistors (Q1, Q1) and a second differential pair of bipolar transistors (Q2, Q2 ), the bases of the first differential pair of bipolar transistors (Q1, Q1) serving as input nodes for the delay stage, the emitters of the first differential pair being coupled to a first current source (CS1) and the collectors being coupled to respective loads (D1, D1; R1, R1) to provide differential output nodes (OUT1, OUT1) of the delay stage, the bases of the second differential pair of bipolar transistors (Q2, Q2) being coupled to respective output nodes of a first differential pair (Q1, Q1) of a delay stage and the emitters of the second differential pair of bipolar transistors (Q2, Q2) being coupled to a variable current source (CS21, CS22,... ) for selectively adjusting the current (IA, IB,... ) through the second differential pair (Q2, Q2 ), the input nodes of each following delay stage (2,..) are coupled to the output nodes of a preceding delay stage, and a common load stage coupled to the collectors of the second differential pairs of bipolar transistors (Q2, Q2) of all delay stages to provide a differential output signal, wherein the amount of phase shift of the output signal is adjusted by adjusting the current through the variable current sources (CS21, CS22,...).