Cascaded Pixel Drive Circuit Layout with Signal-Line Cutouts
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Solution Overview
Problem
Existing display technologies face interference issues due to a large number of crossovers in signal lines, leading to increased parasitic capacitance and signal interference in pixel drive circuits.
Innovation Solution
A pixel drive circuit design with cascaded scan, emission, compensation, and reset drive circuits arranged sequentially, with the scan drive circuit positioned farthest from the pixels, and cutouts at overlapping signal line portions to reduce interference and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If signal lines are arranged in conventional layouts, then device functionality is achieved, but parasitic capacitance and signal interference increase due to crossovers
Solution Approach 1:
The patent applies dimensionality change by transitioning from planar signal line routing to a three-dimensional stacked architecture. Drive circuits for different signal types (scan, emission, compensation, reset) are arranged in vertical layers rather than horizontal planes, allowing signal lines to be routed in different spatial dimensions. This eliminates crossovers and reduces parasitic capacitance while maintaining functional complexity.
Solution Approach 2:
The patent segments the drive circuit functionality into distinct spatial zones. Each drive circuit type (scan, emission, compensation, reset) is separated into different regions or layers, with signal lines for each type routed through dedicated pathways. This segmentation prevents signal line mixing and reduces interference while preserving all necessary device functions.
2Object-affected harmful factors
If drive circuits are arranged in conventional layouts, then all signal lines can be connected, but overlapping areas increase parasitic capacitance
Solution Approach 1:
The patent utilizes vertical stacking to arrange drive circuits in multiple layers along the thickness direction of the substrate. This three-dimensional arrangement reduces the horizontal footprint of the display device while minimizing overlapping areas between signal lines. The stacked configuration allows signal lines to be routed in different vertical planes, reducing parasitic capacitance from overlaps.
3Object-affected harmful factors
If scan drive circuit is positioned closest to pixels, then signal transmission is direct, but interference to pixel emission increases
Solution Approach 1:
The patent employs asymmetric positioning of drive circuits relative to the pixel array. Rather than placing all drive circuits symmetrically around or uniformly close to pixels, the scan drive circuit is positioned at a greater distance or in a different spatial zone compared to other drive circuits. This asymmetric arrangement reduces electromagnetic interference to pixel emission while maintaining efficient signal transmission through optimized routing paths.
Data Source
AI summary
Provided is a pixel drive circuit. The pixel drive circuit includes a plurality of scan drive circuits transmitting gate drive signals to pixels, a plurality of emission drive circuits transmitting emission control signals to the pixels, a plurality of compensation drive circuits transmitting compensation signals to the pixels, and a plurality of reset drive circuits transmitting reset signals to the pixels, which are all cascaded in a pixel column direction. In addition, the scan drive circuit, the emission drive circuit, the compensation drive circuit, and the reset drive circuit corresponding to the same row of pixels are arranged sequentially along a pixel row direction, the scan drive circuit being disposed farthest away from the pixels. Moreover, among signal lines coupled to the pixel drive circuit, a plurality of signal lines is overlapped with each other, and cutouts are provided at the overlapping portions of the plurality of signal lines.