Cascaded Radar Device Architecture for Signal Processing
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Solution Overview
Problem
Current radar systems face inefficiencies in processing radar signals due to the limitations of existing digital signal processing techniques, particularly in utilizing computing performance and memory resources effectively for real-time processing and adaptive control applications.
Innovation Solution
A cascaded device architecture is introduced, comprising a computing engine, radar acquisition unit, timer unit, cascade input/output ports, allowing for efficient data processing by utilizing identical components as both master and slave devices, enabling flexible configuration and distributed processing power for FFT operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple different device designs are used to achieve different processing functions, then functional versatility is improved, but device complexity and manufacturing costs increase
Solution Approach 1:
The patent implements a universal device architecture where a single device type can perform multiple processing functions by being configured in different modes (master or slave) and different numbers within the cascade. The computing engine, radar acquisition unit, and I/O ports are designed to be functionally versatile, allowing the same hardware platform to handle various signal processing tasks including FFT operations, beam forming, and pulse compression through software or configuration changes rather than requiring different hardware designs.
Solution Approach 2:
The patent divides the radar signal processing system into multiple identical device units that can be cascaded in series. Each device segment contains a computing engine, radar acquisition unit, timer unit, and cascade I/O ports. By segmenting the overall processing function across multiple identical modules, the system achieves functional versatility through composition rather than through complex individual device designs, reducing both device complexity and manufacturing costs.
2Productivity
If processing power is increased to improve real-time processing capability, then productivity is improved, but device complexity and resource requirements increase
Solution Approach 1:
The patent segments the processing power across multiple identical device units connected in cascade. Instead of concentrating all processing power in a single complex device, the system distributes FFT operations and other signal processing tasks across multiple computing engines. Each device performs a portion of the overall processing workload, achieving high real-time processing capability through parallel distributed computation while keeping individual device complexity manageable.
Solution Approach 2:
The patent combines multiple identical computing engines and processing units into a unified cascade architecture. By merging the capabilities of multiple devices through cascade connections, the system achieves enhanced real-time processing power that exceeds what a single device could provide, while avoiding the complexity of designing and managing heterogeneous high-power processing systems.
3Ease of manufacture
If memory resources are optimized for a single device, then manufacturing cost is reduced, but processing capacity for large datasets decreases
Solution Approach 1:
The patent segments the memory resources across multiple identical devices in the cascade. Each device maintains its own memory for storing radar signals, intermediate processing results, and operational data. By distributing memory resources across multiple devices rather than concentrating large memory capacity in a single device, the system achieves sufficient total memory capacity for large datasets while keeping individual device memory requirements manageable and manufacturing costs low.
Solution Approach 2:
The patent implements a nested memory architecture where each device in the cascade has its own local memory, and the cascade structure itself provides a hierarchical memory organization. Intermediate processing results can be stored in local device memory and then transferred to subsequent devices in the cascade, creating a distributed nested memory system that provides large total capacity while maintaining economical individual device specifications.
Data Source
AI summary
A device for radar applications includes a computing engine, a radar acquisition unit connected to the computing engine, a timer unit connected to the computing engine, a cascade input port, and a cascade output port. The cascade input port is configured to convey an input signal to the computing engine and the cascade output port is configured to convey an output signal from the computing engine. Further, an according system, a radar system, a vehicle with such radar system and a method are provided.