Cascaded Synchronization Circuit for Glitch-Free Asynchronous Conversion
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Solution Overview
Problem
Existing synchronization circuits often introduce glitches when converting asynchronous signals to synchronous signals, particularly when the asynchronous signal's edges are close to the reference clock signal's edges or have narrow pulses, leading to uncertainty in signal states.
Innovation Solution
A synchronization circuit comprising a signal control circuit, flip-flop circuit, clock enable circuit, and clock control circuit that detects differences between asynchronous and synchronous signals to ensure glitch-free conversion, with a cascaded architecture to fix the phase relationship between the main clock signal and the final synchronous signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional synchronization circuit is used to convert asynchronous signal to synchronous signal, then the conversion function is achieved, but glitches are introduced in the output signal when the asynchronous signal edge is close to the reference clock edge or has narrow pulse
Solution Approach 1:
The synchronization circuit is divided into multiple independent functional modules: a first synchronization submodule that samples the asynchronous signal on the rising edge of the reference clock to generate a first synchronous signal, and a second synchronization submodule that samples the asynchronous signal on the falling edge of the reference clock to generate a second synchronous signal. These two submodules work in parallel and their outputs are combined through logic operations to produce the final synchronous output signal. This segmentation allows each submodule to handle specific timing scenarios, eliminating glitches that would occur in a single synchronous circuit when signal edges are close to clock edges or pulses are narrow.
Solution Approach 2:
The invention introduces an intermediary mechanism using two separate synchronization paths (rising edge path and falling edge path) that act as mediators between the asynchronous input signal and the synchronous output signal. Each path processes the signal independently with appropriate sampling timing, and the intermediary logic combination circuit merges these two processed signals to produce the final output. This intermediary approach prevents direct coupling between the asynchronous signal and the synchronous clock domain, thereby eliminating glitch propagation.
2Device complexity
If a single synchronous circuit is used for signal conversion, then the circuit structure is simple, but the phase relationship between the synchronous signal and the main clock signal cannot be fixed
Solution Approach 1:
The synchronization circuit is divided into multiple independent functional modules: a first synchronization submodule that samples the asynchronous signal on the rising edge of the reference clock to generate a first synchronous signal, and a second synchronization submodule that samples the asynchronous signal on the falling edge of the reference clock to generate a second synchronous signal. These two submodules work in parallel and their outputs are combined through logic operations to produce the final synchronous output signal. This segmentation allows each submodule to handle specific timing scenarios, eliminating glitches that would occur in a single synchronous circuit when signal edges are close to clock edges or pulses are narrow.
Solution Approach 2:
The invention utilizes periodic sampling actions at different phases of the clock cycle. The first synchronization submodule samples on the rising edge (0-degree phase) while the second synchronization submodule samples on the falling edge (180-degree phase) of the reference clock. This periodic action at complementary phases ensures that regardless of when the asynchronous signal transitions occur within the clock period, at least one of the two sampling paths will capture the transition correctly without glitch, thereby fixing the phase relationship between the output synchronous signal and the main clock signal.
Data Source
AI summary
A synchronization circuit and a cascaded synchronization circuit for converting an asynchronous signal into at least one synchronous signal are provided. The synchronization circuit includes a signal control circuit, a flip-flop circuit, a clock enable circuit and a clock control circuit. The flip-flop circuit is coupled to the signal control circuit, the clock enable circuit is coupled to the signal control circuit and the flip-flop circuit, and the clock enable circuit is coupled to the signal control circuit and the flip-flop circuit. The signal control circuit and the clock control circuit can guarantee hold time and setup time is sufficient to allow the flip-flop circuit to output the synchronous signal without glitch regardless of the asynchronous signal.