Cascading Memory Dice Wire Layout for 1600 MHz Signal Stability
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Solution Overview
Problem
Existing memory devices face complexity in wire bonding due to prolonged distances between wires and wire layouts, making them unsuitable for high-frequency operations beyond 1600 MHz.
Innovation Solution
A memory device design featuring a substrate with sequentially cascading memory dices, an 'Ω'-shaped wire layout that connects memory dices and unit address controllers, a processing unit, and a reflective signal absorption unit, significantly reducing distances between wires and components for simplified design and stable operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If direct wire-bonding is used without wire layout design, then flexibility of the procedure is improved, but wire running becomes complex and distances between wires and wire layout are prolonged
Solution Approach 1:
The patent applies preliminary action by pre-designing an optimized wire layout pattern before wire bonding. The wire layout is planned in advance to define optimal paths and connection points, preventing complex wire routing during the actual bonding process. This preliminary planning stage separates the design complexity from the manufacturing flexibility, allowing workers to follow predetermined routes while maintaining procedural flexibility.
Solution Approach 2:
The wire layout acts as an intermediary between the direct wire-bonding process and the final electrical connections. Instead of directly connecting wires between components without guidance, the wire layout serves as a mediating framework that organizes wire paths, reduces complexity, and maintains manufacturing flexibility by providing clear routing instructions.
2Ease of manufacture
If direct wire-bonding without wire layout design is used, then procedure flexibility is improved, but distances between wires and wire layout are prolonged
Solution Approach 1:
By pre-planning the wire layout with optimized paths and connection points, the patent minimizes wire lengths before the actual bonding process. The preliminary design stage allows for calculation and optimization of wire routes, ensuring shortest possible paths while maintaining procedural flexibility during manufacturing.
Solution Approach 2:
The patent applies parameter changes by optimizing geometric parameters of wire paths, connection point locations, and routing angles. These parameter optimizations directly reduce wire lengths and distances between wires and components, while the flexible procedure allows adaptation to different parameter sets for various device configurations.
3Device complexity
If prolonged wire distances are used, then device structure is simpler, but operation under high frequency (more than 1600 MHz) is not suitable
Solution Approach 1:
The pre-designed wire layout optimizes signal path lengths and impedance matching before high-frequency operation. By planning wire routes and connection points in advance, the patent minimizes signal degradation and reflection issues that would otherwise limit operating frequency, enabling stable operation above 1600 MHz while maintaining relatively simple device structure.
Solution Approach 2:
The patent applies parameter changes by optimizing electrical parameters such as wire length, trace geometry, and connection point locations within the wire layout. These parameter optimizations reduce signal loss and impedance discontinuities, enabling the device to operate at high frequencies (above 1600 MHz) without requiring complex shielding or filtering structures.
4Productivity
If wires are not optimized in design, then design process is faster, but wire lengths are prolonged and signal stability at high frequency is compromised
Solution Approach 1:
By implementing a pre-planned wire layout with optimized paths and connection points, the patent achieves both fast design and reliable signal transmission. The preliminary design stage establishes optimal wire routing that minimizes length and maximizes signal integrity, allowing rapid manufacturing while ensuring stable high-frequency operation. This eliminates the trade-off between design speed and signal reliability.
Solution Approach 2:
The wire layout serves as an intermediary that bridges the gap between rapid design processes and high-reliability signal transmission. It provides a predetermined framework that accelerates manufacturing while simultaneously optimizing electrical characteristics for stable signal operation at high frequencies, resolving the contradiction between design productivity and signal reliability.
Data Source
AI summary
A memory device is provided. The memory device is used for data transmission at around 1600 megahertz (MHz). A wire layout is used to sequentially cascade memory dices with greatly shortened distances between the wire layout and the memory dices. At the same time, distances between the wire layout and UA controllers are shortened as well for effectively simplifying the design of wires.