Cascading Start Pulses in Matrix Display Timing Controllers
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Solution Overview
Problem
Conventional matrix display devices require a counter circuit for generating a vertical clock, necessitating a register or memory to hold the resolution in the timing controller, limiting flexibility and increasing circuit complexity.
Innovation Solution
A matrix display device with a timing controller that cascades unit start pulses among video signal line drive circuits and controls the duty ratio of the vertical clock, eliminating the need for a counter circuit and external memory to hold the resolution, thereby simplifying the circuit configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a counter circuit is used to generate a vertical clock for vertical scan, then the vertical scan can be controlled, but the circuit complexity and device scale increase
Solution Approach 1:
The patent extracts the vertical clock generation function from a dedicated counter circuit and relocates it to the video signal line drive circuits. Specifically, the unit start pulses from the video signal line drive circuits are cascaded to generate the vertical clock signal, eliminating the need for a separate counter circuit in the timing controller and reducing overall circuit complexity while maintaining reliable vertical scan control
Solution Approach 2:
The video signal line drive circuits are given multiple functions: they not only drive the video signal lines but also generate the vertical clock signal through cascading unit start pulses. This multi-functionality eliminates the need for dedicated separate circuits for vertical clock generation, thereby reducing device complexity while ensuring proper vertical scan operation
2Adaptability or versatility
If a register or memory is provided to hold the resolution parameter, then the timing controller can control various resolutions, but the device complexity and integration difficulty increase
Solution Approach 1:
The patent removes the resolution parameter storage function from the timing controller by extracting it from registers or external memory. Instead, the resolution information is implicitly handled through the cascading of unit start pulses from the video signal line drive circuits, eliminating the need for dedicated storage elements and reducing circuit complexity while maintaining resolution adaptability
Solution Approach 2:
The video signal line drive circuits self-generate the vertical clock signal through cascading unit start pulses, eliminating the need for the timing controller to store or manage resolution parameters separately. This self-service mechanism allows the system to adapt to various resolutions without requiring external memory or complex internal registers in the timing controller
3Adaptability or versatility
If external memory is provided for holding resolution, then the timing controller can support multiple resolutions, but the device scale and integration difficulty increase
Solution Approach 1:
The patent extracts the resolution storage function from external memory and integrates it into the signal generation process itself. The unit start pulses from the video signal line drive circuits inherently contain the timing information needed for various resolutions, eliminating the need for external memory and reducing the overall device scale while maintaining resolution versatility
Solution Approach 2:
The patent merges the vertical clock generation function with the video signal line drive circuits by cascading unit start pulses. This integration eliminates the need for separate external memory components, combining multiple functions into existing circuits and thereby reducing device scale while preserving the ability to support multiple resolutions
Data Source
AI summary
In a plurality of source drivers, a unit start pulse inputted/outputted to/from the source drivers is cascaded between an ante-stage source driver and a post-stage source driver, a horizontal start pulse outputted from a timing controller is inputted to a first-stage source driver, and the duty ratio of a vertical clock is controlled by one of the plurality of cascaded unit start pulses. In a matrix display device, it is thereby possible to provide a timing controller having a simple circuit configuration which needs no counter circuit for generating a vertical clock to be outputted to a gate driver.