Cascode Amplifier Input Stage for Bias Current Cancellation

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Solution Overview

Problem

Operational amplifiers with bipolar input transistors face challenges in effectively canceling input bias current, often requiring replica circuits or manufacturing trimming for accurate cancellation.

Innovation Solution

The integration of bipolar cascode transistors and current mirror circuits that mirror and subtract base currents from the input transistors, eliminating mismatch effects and providing up to a 100x reduction in input bias current without the need for trimming or replica circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If replica circuits or manufacturing trimming are used to cancel input bias current, then input bias current cancellation accuracy is improved, but device complexity and manufacturing cost increase

Engineering Contradiction:
Improveinput bias current cancellation accuracyVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extracts and separates the bias current cancellation function from the main amplifier circuit by using dedicated current mirror circuits that replicate and subtract the bias current paths. This allows accurate cancellation without requiring complex replica circuits or trimming mechanisms, as the cancellation is achieved through the inherent current mirroring action of the cascode transistor configurations.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The cascode transistor configuration serves multiple functions simultaneously: it provides the necessary current mirroring for bias cancellation, maintains the amplifier's voltage gain, and ensures proper biasing of the input transistors. This multi-functionality eliminates the need for separate replica circuits or trimming components, reducing overall device complexity while achieving accurate bias current cancellation.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Measurement precision

If replica circuits are used for bias current cancellation, then cancellation accuracy is improved, but manufacturing process complexity increases

Engineering Contradiction:
Improvebias current cancellation accuracyVSAvoidmanufacturing process simplicity
Core Design Contradiction:
Measurement precisionVSEase of manufacture

Solution Approach 1:

The circuit achieves self-service bias current cancellation through the natural current mirroring behavior of the cascode transistor configuration. The circuit automatically replicates and subtracts the bias current without requiring external trimming mechanisms or complex replica circuits, making the manufacturing process simpler while maintaining high cancellation accuracy.

Inventive Principle:
Principle #25Self-service

3Object-generated harmful factors

If cascode transistors and current mirror circuits are integrated for bias cancellation, then input bias current is reduced by up to 100x, but circuit complexity increases

Engineering Contradiction:
Improveinput bias currentVSAvoidcircuit structure
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The patent merges the bias cancellation function with the amplifier's input stage by integrating cascode transistors and current mirror circuits into the existing differential pair configuration. This unified approach achieves up to 100x reduction in input bias current while avoiding the need for separate, complex cancellation circuits, as the cancellation is accomplished through the inherent structure of the integrated amplifier stage.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10992271B2Amplifier with input bias current cancellation
Publication Date: 2021.04.27 TEXAS INSTRUMENTS INC
  • US10992271B2 patent drawing
  • US10992271B2 patent drawing
  • US10992271B2 patent drawing

AI summary

An amplifier includes a first input transistor, a second input transistor, a first cascode transistor, a second cascode transistor, a first current mirror circuit, and a second current mirror circuit. The first input transistor is coupled to a first input terminal. The second input transistor is coupled to a second input terminal and the first input transistor. The first cascode transistor is coupled to the first input transistor. The second cascode transistor is coupled to the second input transistor and the first cascode transistor. The first current mirror circuit is coupled to the first cascode transistor, the second cascode transistor, and the first input terminal. The second current mirror circuit is coupled to the first cascode transistor, the second cascode transistor, and the second input terminal.