Cascode Power Amplifier Bypass Layout for Stable High Gain

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Solution Overview

Problem

Multi-stage power amplifiers face challenges in achieving high lineup efficiency due to limitations in gain of the final stage, particularly in solid-state technology and packaging, which affects overall efficiency and output power stability.

Innovation Solution

Implementing a cascode structure at each unit cell of the power amplifier, minimizing parasitic inductance between the gate and bypass capacitor, and optimizing bypass capacitance to enhance gain and stability, while maintaining output power and stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a cascode structure is implemented at each unit cell to improve gain and lineup efficiency, then the lineup efficiency improves by up to 4 percentage points, but parasitic inductance between the gate and bypass capacitor degrades stability

Engineering Contradiction:
Improvelineup efficiencyVSAvoidamplifier stability
Core Design Contradiction:
ProductivityVSStability of the object's composition

Solution Approach 1:

The patent extracts and eliminates the parasitic inductance element from the circuit by removing the inductor component that was coupled between the bypass capacitor and the gate. This leaves only the minimal parasitic inductance inherent in the capacitor connection, thereby resolving the stability issue while preserving the gain and efficiency improvements from the cascode structure.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the capacitance value of the bypass capacitor to optimize the resonant frequency. By selecting a capacitance that resonates with the remaining parasitic inductance at a frequency substantially higher than the desired operating frequency, the circuit maintains stability in the operating band while benefiting from the cascode configuration's improved gain and efficiency.

Inventive Principle:
Principle #35Parameter changes

2Power

If bypass capacitance is optimized to enhance gain, then the gain and lineup efficiency improve, but insufficient bypass capacitance degrades stability

Engineering Contradiction:
Improveamplifier gainVSAvoidamplifier stability
Core Design Contradiction:
PowerVSStability of the object's composition

Solution Approach 1:

The patent optimizes the bypass capacitance parameter by selecting a specific capacitance value that resonates with the parasitic inductance at a frequency substantially higher than the desired operating frequency. This parameter optimization enables the circuit to achieve high gain through the cascode structure while maintaining stability by pushing the resonant frequency out of the operating band.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If inductor components are used in the bypass circuit, then impedance matching is improved, but the inductor introduces additional parasitic inductance that degrades stability

Engineering Contradiction:
Improveimpedance matchingVSAvoidamplifier stability
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent removes the inductor component from the bypass circuit, extracting the source of excess parasitic inductance. This elimination resolves the stability problem caused by the inductor's parasitic effects while the bypass capacitor alone provides sufficient impedance matching functionality at the operating frequency.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in a significant improvement of lineup efficiency by up to 4 percentage points without modifying solid-state material, achieving higher gain and stability in power amplifiers for wireless communication applications.

Implementation Method 1

The capacitor has a capacitance sized to resonate with the parasitic inductance at a resonant frequency substantially higher than a desired frequency of operation of the power amplifier cell

Methodology Applied
Scientific EffectResonance: Resonance

Data Source

PatentUS20240243709A1Methods and techniques to improve stability of cascode amplifiers and enhance lineup efficiency in multi-stage power amplifiers
Publication Date: 2024.07.18 QORVO US INC
  • US20240243709A1 patent drawing
  • US20240243709A1 patent drawing
  • US20240243709A1 patent drawing

AI summary

A power amplifier cell is disclosed having a first transistor with a first terminal coupled to ground, a second terminal, and a first control terminal. A second transistor has a third terminal coupled to the second terminal, a fourth terminal, and a second control terminal. Further included is a capacitor having a first plate coupled directly to the second control terminal and a second plate coupled to the ground. As such, there is no intervening inductor component coupled between the first plate and the second control terminal, leaving only parasitic inductance between the first plate and the second control terminal. The capacitor has a capacitance sized to resonate with the parasitic inductance at a resonant frequency substantially higher than a desired frequency of operation of the power amplifier cell.