Cascode Amplifier Feedback for Distortion and Impedance Matching

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Solution Overview

Problem

Existing cascode-connected amplifier circuits for high-frequency signals in mobile communication devices face challenges in achieving sufficient distortion characteristics and impedance matching, particularly with transistors of different gate widths, leading to inadequate performance in noise figure and current consumption over a wide dynamic range.

Innovation Solution

The proposed amplifier circuit configuration includes a first and second transistor coupled in parallel, with a third transistor cascoded with either of them, and feedback circuits that feed back high-frequency signals to improve distortion characteristics and impedance matching by optimizing the gate width and length ratios and using feedback circuits to adjust bias voltages based on input signal intensity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If two transistors of different gate widths are used in parallel amplifier circuits with cascode connection, then amplification characteristic and noise characteristic are improved over wide dynamic range, but distortion characteristic becomes insufficient especially with smaller gate width transistor

Engineering Contradiction:
Improveamplification characteristic and noise characteristicVSAvoiddistortion characteristic
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies feedback by connecting a feedback capacitor between the drain and gate of the smaller gate width transistor. This feedback mechanism reduces the distortion characteristic issues that arise from using transistors of different gate widths in parallel, while preserving the benefits of improved amplification and noise characteristics over wide dynamic range.

Inventive Principle:
Principle #23Feedback

2Use of energy by moving object

If two transistors of different gate widths operate in exclusive manner, then current consumption is reduced over wide dynamic range, but input/output impedance fluctuates making impedance matching difficult

Engineering Contradiction:
Improvecurrent consumptionVSAvoidimpedance matching
Core Design Contradiction:
Use of energy by moving objectVSEase of operation

Solution Approach 1:

The feedback capacitor connected between drain and gate of the smaller gate width transistor helps stabilize the input and output impedance. This stabilization occurs because the feedback mechanism compensates for impedance fluctuations that arise when transistors operate in exclusive manner, thereby facilitating impedance matching with external circuits while maintaining low current consumption.

Inventive Principle:
Principle #23Feedback

3Speed

If cascode-connected transistors of different gate widths are used, then frequency characteristic is improved by reducing Miller effect, but distortion characteristic remains insufficient

Engineering Contradiction:
Improvefrequency characteristicVSAvoiddistortion characteristic
Core Design Contradiction:
SpeedVSObject-generated harmful factors

Solution Approach 1:

The patent introduces feedback through a capacitor connected between the drain and gate of the smaller gate width transistor in the cascode configuration. This feedback mechanism specifically addresses the distortion characteristic issue while preserving the frequency characteristic improvements achieved through cascode connection and Miller effect reduction.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11342891B2Amplifier circuit
Publication Date: 2022.05.24 MURATA MFG CO LTD
  • US11342891B2 patent drawing
  • US11342891B2 patent drawing
  • US11342891B2 patent drawing

AI summary

An amplifier circuit (1) includes a FET (10) having a source terminal (S1), a drain terminal (D1), and a gate terminal (G1), a FET (20) having a source terminal (S2), a drain terminal (D2), and a gate terminal (G2) and coupled in parallel with the FET (10), a FET (30) having a source terminal (S3) coupled to the drain terminals (D1 and D2), a drain terminal (D3), and a gate terminal (G3) and cascoded with the FETs (10 and 20), and feedback circuits (21 and 22) configured to feed back to the gate terminal (G2) a high frequency signal outputted from the source terminal (S2) or the drain terminal (D2).