Parallel Gate-Line Cascode Amplifier for Lower Wiring Resistance
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Solution Overview
Problem
Cascode amplifiers in mobile communication devices experience a reduction in output power due to increasing wiring resistance as the total gate width increases, leading to decreased power gain and output power.
Innovation Solution
The implementation of a cascode amplifier design with multiple parallel lines connected to the gates of transistors and a capacitance between one end of these lines and ground, reducing wiring resistance and minimizing differences in operating conditions between cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the total gate width of the cascode amplifier is increased to increase output power, then the output power should increase, but the wiring resistance of the gate line increases which prevents the output power from increasing
Solution Approach 1:
The gate line is divided into multiple parallel lines (at least two) connecting the gates of the second transistors to ground. This segmentation reduces the equivalent resistance of the gate line by providing multiple current paths, thereby reducing the energy loss due to wiring resistance while maintaining the required gate width for high output power.
2Power
If the total gate width is increased to increase output power, then more transistors are needed, but the increased wiring resistance causes the increase in output power to fail
Solution Approach 1:
The gate line is divided into multiple parallel lines (at least two) connecting the gates of the second transistors to ground. This segmentation reduces the equivalent resistance of the gate line by providing multiple current paths, thereby reducing the energy loss due to wiring resistance while maintaining the required gate width for high output power.
3Device complexity
If a single gate line is used to connect all gate terminals, then the structure is simple, but the resistance of the gate line increases with total gate width
Solution Approach 1:
The gate line is divided into multiple parallel lines (at least two) connecting the gates of the second transistors to ground. This segmentation reduces the equivalent resistance of the gate line by providing multiple current paths, thereby reducing the energy loss due to wiring resistance while maintaining the required gate width for high output power.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively minimizes the reduction in output power due to wiring resistance, allowing for increased gate width without a corresponding decrease in output power, and reduces differences in operating conditions between cells.
Implementation Method 1
a capacitance connected between one end of the second line and ground
Data Source
AI summary
A cascode amplifier includes: first transistors; second transistors cascode-connected with respective first transistors; a first line connected at spaced points to control terminals of the first transistors; a second line connected at spaced points to control terminals of the second transistors; and a capacitance connected between one end of the second line and ground. The second line includes at least two lines connected in parallel with each other.