Differential Cascode Amplifier Layout for Lower Parasitic Capacitance

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Solution Overview

Problem

High parasitic capacitance in amplifiers used in wireless communications at extremely high frequencies leads to degraded output power, gain, efficiency, linearity, and stability, while neutralizing capacitors increase the amplifier's footprint, making it challenging to fit within space-constrained devices.

Innovation Solution

An amplifier with a differential cascode configuration, where channel terminal regions form a floating region with minimal electrical contacts, reducing parasitic capacitance and maintaining a compact footprint by integrating capacitors within the layout without increasing size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If neutralizing capacitors are added to reduce parasitic capacitance, then parasitic capacitance is reduced, but the amplifier footprint increases

Engineering Contradiction:

Improveparasitic capacitanceVSAvoidamplifier footprint

Core Design Contradiction:

Object-affected harmful factorsVSArea of stationary object

Solution Approach 1:

The patent extracts and eliminates the need for external neutralizing capacitors by reconfiguring the amplifier circuit. The differential cascode configuration with floating node design inherently compensates for parasitic capacitance effects without requiring separate capacitor components, thus reducing the amplifier footprint while maintaining performance.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent merges the functions of parasitic capacitance compensation and signal amplification into a single integrated circuit configuration. The floating node in the differential cascode structure performs both the amplification function and the parasitic capacitance cancellation function simultaneously, eliminating the need for separate neutralizing capacitors.

Inventive Principle:

Principle #5Merging (Combining)

2Productivity

If higher frequencies are used to increase transmission rates, then transmission rates and throughput increase, but path loss increases

Engineering Contradiction:

Improvetransmission rateVSAvoidpath loss

Core Design Contradiction:

ProductivityVSLoss of energy

Solution Approach 1:

The patent changes the operating parameters of the amplifier by using a differential cascode configuration optimized for millimeter-wave frequencies. This configuration provides higher gain and better linearity at frequencies above 24 GHz, compensating for the increased path loss and enabling effective high-rate transmission despite the energy losses.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS12401326B2Reducing parasitic capacitance

Publication Date: 2025.08.26 QUALCOMM INC

AI summary

An apparatus is disclosed for reducing parasitic capacitance. In an example aspect, an apparatus includes an amplifier having a differential cascode configuration. Each stack of the amplifier includes a first transistor configured to operate as an input stage and a second transistor configured to operate as a cascode stage. The first and second transistors each include two channel terminal regions having a doping type that is uniform across the two channel terminal regions. Surfaces of first channel terminal regions of the first and second transistors abut a first and second quantity of electrical contacts, respectively. Second channel terminal regions of the first and second transistors form a floating region at a floating node. Each of the first quantity of electrical contacts and the second quantity of electrical contacts is greater than a third quantity of electrical contacts abutting a surface of the floating region.