Cascode Bandgap Reference Circuit for High-PSR AMOLED Biasing
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Solution Overview
Problem
Conventional bandgap reference circuits face limitations in power supply rejection (PSR) performance due to coupling between the supply voltage and collector terminal of bipolar transistors, leading to current mismatches and instability in bandgap voltage, especially in applications with variable supply voltages like AMOLED displays.
Innovation Solution
A single-stage bandgap reference circuit architecture is introduced, utilizing a cascode arrangement of NMOS transistors to decouple the collector terminals of bipolar transistors from the supply voltage, and employing a bandgap-referred voltage to manage base currents, thereby improving PSR performance and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bandgap reference circuit architecture is used, then circuit simplicity is maintained, but PSR performance deteriorates due to coupling between supply voltage and collector terminal
Solution Approach 1:
The patent introduces cascode transistors (N1, N2) as intermediary elements between the current generators and the bipolar transistors. These cascode devices act as mediators that block the direct coupling path between supply voltage variations and the collector terminals of the bipolar transistors, thereby improving PSR performance while maintaining a single-stage architecture.
2Stability of the object's composition
If supply voltage coupling to collector terminal is present, then circuit operation is simplified, but current mismatch occurs leading to bandgap voltage instability
Solution Approach 1:
The cascode transistors N1 and N2 serve as intermediary devices that decouple the supply voltage from the collector terminals of bipolar transistors Q1 and Q2. This intermediary structure prevents supply voltage variations from causing current mismatches, thereby stabilizing the bandgap voltage without requiring complex multi-stage architectures.
3Reliability
If two-stage bandgap architecture is used, then PSR performance is improved, but area and current consumption increase
Solution Approach 1:
The patent merges the decoupling function and the bandgap reference generation into a single integrated stage. The cascode transistors are incorporated within the same stage as the bipolar transistors, eliminating the need for a separate pre-regulator stage. This merging achieves improved PSR performance while reducing current consumption and area compared to two-stage architectures.
4Reliability
If cascode arrangement is added to decouple collector terminals, then PSR performance improves, but circuit complexity increases
Solution Approach 1:
The patent combines the cascode decoupling structures with the bandgap reference generation in a single integrated stage. The cascode transistors N1 and N2 are directly integrated with the bipolar transistors Q1 and Q2, achieving PSR improvement without requiring a separate decoupling stage or multi-stage architecture.
Data Source
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AI summary
A bandgap circuit (10), for use in AMOLED display devices, for instance, comprises a supply node (VSUPPLY) as well as a first bipolar transistor (Q1) and a second bipolar transistor (Q2), having their base terminals jointly coupled to a bandgap node to provide a bandgap voltage (VBG) at the bandgap node. A first current generator (121a, 121b) and a second current generator (122a, 122b) coupled to the supply node (VSUPPLY) are provide to supply a first current (I1) and a second current (I2) to a first circuit node (A) and a second circuit node (B), with the current (I2) of the second current generator mirroring the current (I1) of the first current generator. A third circuit node (D) is coupled to the current flow path through the first bipolar transistor (Q1) via a first resistor (R1) and coupled to ground (GND) via a second resistor (R2), respectively. The third circuit node (D) is also coupled to the current flow path through the second bipolar transistor (Q2) so that the second resistor (R2) is traversed by a current which is the sum of the currents (I1, I2) through the bipolar transistors (Q1 and Q2). Intermediate the current generators (121a, 121b; 122a, 122b) and the bipolar transistors (Q1, Q2) a decoupling stage (200) is provided comprising a first (N1) and a second (N2) cascode decoupling transistor having their control terminals jointly coupled to a fourth circuit node (C) sensitive to the ground-referred bandgap voltage (VBG).