Cascode Amplifier Bias Circuit With Closed-Loop Current Matching
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Solution Overview
Problem
Silicon-based CMOS cascode amplifier circuits face challenges in designing bias circuits that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, particularly due to poor output resistance characteristics and the 'floating body' effect, which affects RF performance and adaptability to changing RF environments.
Innovation Solution
The implementation of a cascode reference circuit with a closed loop bias control circuit that dynamically adjusts the gate bias voltage to maintain a consistent current multiple, accommodating arbitrary supply voltage variations and improving output resistance by matching drain and gate voltages across stages, while also allowing for digital programmability to adapt to changing RF conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If silicon-based CMOS transistors with short channel lengths are used, then fast RF response is achieved, but poor output resistance characteristics occur due to the influence of drain voltage on the gate
Solution Approach 1:
The transistor gate is divided into two independent gates (first gate and second gate) that can be controlled separately. This segmentation allows independent optimization of RF response (through the first gate) and output resistance (through the second gate), resolving the contradiction between fast RF response and poor output resistance characteristics
Solution Approach 2:
The dual-gate transistor structure enables the same device to perform multiple functions: the first gate controls RF signal amplification while the second gate independently controls output resistance. This multi-functionality allows simultaneous optimization of both RF response speed and output resistance characteristics without requiring separate devices
2Device complexity
If common open-loop bias techniques such as current mirrors are used, then biasing is simplified, but large mismatch between reference device current and output device current occurs
Solution Approach 1:
A feedback mechanism is implemented where the second gate of the output transistor receives a controlled voltage that adjusts the output current to match the reference current. This feedback loop compensates for mismatches and ensures accurate current mirroring while maintaining reasonable circuit complexity
Solution Approach 2:
The invention changes the biasing parameters by applying different voltages to the first and second gates independently. By adjusting the second gate voltage dynamically, the output current can be precisely controlled to match the reference current, improving current matching accuracy without significantly increasing circuit complexity
3Use of energy by moving object
If the DC supply voltage is actively modified to optimize operation at different power levels, then power optimization is achieved, but bias circuit tolerance to voltage variations deteriorates
Solution Approach 1:
The bias circuit is designed to be dynamic rather than static, with the second gate voltage being actively adjusted in response to supply voltage variations. This dynamic adaptation allows the bias circuit to maintain tolerance to voltage variations while still enabling power optimization through active supply voltage modification
Solution Approach 2:
The invention changes the bias voltage parameters dynamically based on supply voltage conditions. By adjusting the second gate voltage in response to supply voltage changes, the circuit maintains proper biasing and tolerance across different power levels, enabling both power optimization and voltage variation tolerance
4Strength
If transistor stack height is increased to handle higher voltages, then voltage handling capability is improved, but bias circuit design complexity increases due to floating body effects
Solution Approach 1:
The invention extracts the body effect influence by separately controlling the second gate, which directly affects the output resistance and current. By taking out the body effect from the primary control mechanism and handling it independently through the second gate, the bias circuit design becomes more manageable even with increased transistor stack height
Data Source
AI summary
Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.