Cascode Amplifier Bias Control for Multi-Gain IP3 Linearity
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Solution Overview
Problem
Existing RF amplifiers, particularly those in cascode configuration, face challenges in optimizing linearity performance across different gain-states without increasing design complexity, as the input transistor dominates non-linearity in low gain-states and the output transistor in high gain-states.
Innovation Solution
The solution involves controlling the drain-to-source voltage of the input and output transistors by adjusting the gate voltage, specifically increasing the drain-to-source voltage of the input transistor in low gain-states and the output transistor in high gain-states, using a gain decoder and bias control circuit to optimize the third-order intercept point (IP3) without requiring adjustable/switchable elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the amplifier is designed to operate in multiple gain-states, then the amplifier can support different modes of operation and frequency bands, but the linearity performance (IP3) cannot be optimized for both low gain-state and high gain-state simultaneously
Solution Approach 1:
The patent applies local quality by differentiating the biasing conditions for different transistors based on their specific roles and the operating gain-state. In low gain-state, the input transistor is biased for optimal linearity while the output transistor is biased for adequate gain. In high gain-state, the biasing is adjusted to optimize the output transistor's contribution to linearity. This localized optimization of transistor characteristics resolves the contradiction between multi-gain-state adaptability and consistent linearity performance.
Solution Approach 2:
The patent implements dynamic biasing control where the bias voltages applied to the gates of input and output transistors are dynamically adjusted based on the desired gain-state. A control circuit modifies the bias conditions in real-time according to the operating mode, enabling the amplifier to adapt its linearity characteristics to match the current gain-state requirements. This dynamic adjustment resolves the contradiction by making linearity optimization state-dependent rather than fixed.
2Reliability
If adjustable or switchable elements are added to optimize IP3 for different gain-states, then linearity performance can be improved, but the design complexity increases
Solution Approach 1:
The patent changes the electrical parameters (bias voltages) of existing transistors to optimize IP3 for different gain-states, rather than adding physical adjustable or switchable elements. By modifying the gate bias voltages of the input and output transistors based on the operating state, the patent achieves linearity optimization through parameter adjustment alone. This approach improves IP3 performance while avoiding the increased design complexity that would result from adding switches, attenuators, or other adjustable components.
3Reliability
If the drain-to-source voltage of the input transistor is increased in low gain-state, then the third-order intercept point (IP3) is optimized, but the drain-to-source voltage of the output transistor decreases
Solution Approach 1:
The patent dynamically adjusts the drain-to-source voltages of both input and output transistors based on the operating gain-state. In low gain-state, the input transistor's Vds is increased to optimize its linearity and IP3 contribution, while the output transistor's Vds is reduced. In high gain-state, this relationship is reversed. This dynamic voltage allocation resolves the contradiction by making the voltage distribution adaptive to the current operating state rather than fixed, allowing each transistor to contribute optimally to IP3 in its respective gain-state context.
4Reliability
If the drain-to-source voltage of the output transistor is increased in high gain-state, then the third-order intercept point (IP3) is optimized, but the drain-to-source voltage of the input transistor decreases
Solution Approach 1:
The patent implements dynamic voltage distribution where the drain-to-source voltages of input and output transistors are adjusted based on the operating gain-state. In high gain-state, the output transistor's Vds is increased to optimize its linearity performance and IP3 contribution, while the input transistor's Vds is reduced. This dynamic allocation resolves the contradiction between optimizing IP3 in high gain-state and maintaining adequate voltage for the input transistor by making the voltage distribution state-dependent.
Data Source
AI summary
Methods and devices for amplifying an input RF signal according to at least two gain-states is described. According to one aspect, a multi gain amplifier circuit including a low noise amplifier having a stack of transistors is used for amplification of the input RF signal. When switching from a low gain-state to a high gain-state, the drain-to-source voltage of the output transistor of the stack is increased to affect region of operation of the output transistor, and thereby reduce non-linearity at the output of the amplifier. When switching from the high gain-state to the low gain-state, the drain-to-source voltage of the input transistor of the stack is increased to affect region of operation of the input transistor, and thereby reduce non-linearity at the output of the amplifier.