Cascode Voltage Circuit With Equal Ramp Biasing for Latch-Up Prevention
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Solution Overview
Problem
Conventional cascode voltage generation circuits for integrated circuits face issues such as high power consumption, area usage, and risk of latch-up due to unequal ramp rates of intermediate voltages, which can lead to transistor stress and reliability concerns.
Innovation Solution
A cascode voltage generating circuit employing switching elements and a controller to manage intermediate voltage levels, ensuring equal ramp rates and reduced power consumption by switching between high and low voltage operation modes, utilizing transistors to couple nodes to ground and supply voltage accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional cascode voltage generation circuits are used to bias transistors within SOA limits, then transistor reliability is improved, but power consumption and circuit area increase
Solution Approach 1:
The patent combines multiple voltage generation functions into a single integrated circuit block. The cascode voltage generation circuit generates both 2/3 VDD and 1/3 VDD voltages simultaneously using shared transistors and control logic, eliminating the need for separate voltage generation circuits and reducing overall power consumption while maintaining transistor reliability protection
Solution Approach 2:
The control logic circuit serves multiple functions: it controls the switching of both first and second switching elements, generates appropriate bias voltages for different operating modes (read, program, erase), and ensures proper voltage level coordination across different operational states, thereby reducing the need for additional dedicated control circuits
2Reliability
If conventional cascode voltage generation circuits are used to ensure proper voltage levels, then transistor stress is reduced, but circuit area increases
Solution Approach 1:
The patent merges the generation of 2/3 VDD and 1/3 VDD voltages into a single circuit implementation. The first and second switching elements share common control signals and are integrated within the same circuit block, reducing the total area required compared to separate voltage generation circuits while maintaining proper voltage levels for transistor stress protection
Solution Approach 2:
The circuit is segmented into distinct switching elements (first switching element for 2/3 VDD, second switching element for 1/3 VDD) that can be independently controlled through the control logic. This segmentation allows for optimized area usage while maintaining the ability to provide appropriate voltage levels for protecting transistors from stress
3Reliability
If intermediate voltages are generated using conventional methods, then cascode biasing is achieved, but unequal ramp rates cause latch-up risk
Solution Approach 1:
The control logic circuit monitors the operational mode (read, program, erase) and adjusts the switching of the first and second switching elements accordingly. This feedback mechanism ensures that voltages ramp at equal rates during high voltage operations by coordinating the activation and deactivation of switching elements based on the current operational state, preventing latch-up while managing circuit complexity
4Use of energy by moving object
If switching elements are used to couple nodes to ground and supply voltage, then static current consumption is reduced, but control complexity increases
Solution Approach 1:
The switching elements are controlled to switch periodically based on the operational mode (read, program, erase). The control logic activates switching elements only when needed for specific operations, keeping them in high-impedance or off states during other operations. This periodic switching reduces static current consumption while the control logic manages the complexity of coordinating these switching actions across different operational states
Data Source
AI summary
A cascode voltage generating circuit and method are provided. The circuit includes four switching elements. In a high voltage operation mode, the first and second switching elements, respectively, couple a first intermediate voltage input node to a first intermediate voltage output node, and a second intermediate voltage input node to a second intermediate voltage output node. In a low voltage operation mode, the third switching element couples the first and second intermediate voltage input nodes to a ground reference voltage level, and the fourth switching element couples the first and second intermediate voltage output nodes to a supply voltage level.