Cascode Differential Reference Buffer for Interleaved ADC Ripple Control
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Solution Overview
Problem
High-speed Analog-to-Digital Converters (ADCs) require a reference buffer that can provide low impedance and high current drive to quickly charge and discharge capacitors, which existing bandgap references cannot efficiently achieve, especially for high-resolution and time-interleaved ADCs, necessitating a solution that minimizes ripple error and power supply rejection.
Innovation Solution
A parallel multi-channel cascode Class-A differential reference buffer using source follower transistors with negative feedback to generate low impedance and high current drive voltage references, which can be mirrored across multiple parallel legs to reduce crosstalk and improve signal rejection, and optionally utilizing self-biasing or cascode configurations to optimize power consumption and impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a bandgap reference is used to generate reference voltages, then high precision is achieved, but the current drive capability is insufficient for high-speed ADC operation
Solution Approach 1:
The reference buffer is divided into multiple parallel legs (first leg, second leg, third leg, fourth leg) where each leg contains source follower transistors that independently contribute to the total current drive capability while maintaining the precision reference voltage from the bandgap reference
Solution Approach 2:
Source follower transistors are introduced as intermediary components between the bandgap reference and the ADC capacitor array. These source followers act as buffer stages that provide high current drive capability while preserving the precision reference voltage, effectively mediating between the precision reference and the high-speed ADC requirements
2Speed
If higher current drive is provided to quickly charge and discharge capacitors, then high sampling speed is achieved, but ripple error and power supply rejection deteriorate
Solution Approach 1:
Negative feedback is applied through operational amplifiers (first op amp, second op amp) that monitor the reference voltages and adjust the gate voltages of the source follower transistors accordingly. This feedback mechanism stabilizes the reference voltages against ripple and power supply variations, maintaining precision even while providing high current drive for fast sampling
Solution Approach 2:
The source follower transistors are pre-configured in parallel legs with appropriate sizing to provide the necessary current drive capability before the ADC sampling operation begins. This preliminary preparation ensures that when sampling occurs, the required current is already available, enabling high sampling speed without causing ripple errors
3Reliability
If multiple parallel legs are used to reduce crosstalk between channels, then channel isolation is improved, but device complexity increases
Solution Approach 1:
The reference buffer is segmented into multiple parallel legs (first leg with first source follower, second leg with second source follower, third leg with third source follower, fourth leg with fourth source follower), where each leg is dedicated to specific ADC channels. This segmentation provides channel isolation to reduce crosstalk while maintaining a modular structure that manages complexity through repetition of standardized units
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high-speed, low-ripple, and low-noise reference buffering with improved power supply rejection, supporting high sampling rates and reducing crosstalk between ADC channels, while maintaining low power consumption and compatibility with reduced power-supply voltages.
Implementation Method 1
A parallel multi-channel cascode Class-A differential reference buffer using source follower transistors with negative feedback to generate low impedance and high current drive voltage references
Implementation Method 2
optionally utilizing self-biasing or cascode configurations to optimize power consumption and impedance
Data Source
AI summary
A reference buffer has many legs each with an upper transistor, a lower transistor, and a resistor or current source as a tail device in series. The source or emitter of the upper (lower) transistor generates an upper (lower) reference voltage. This source follower transistor configuration has a low output impedance and high current. The gate or base of the upper (lower) transistors are driven by a first (second) control node. A control leg has an upper transistor, a lower transistor, and a tail device in series. The source and gate, or emitter and base, are connected together for the upper and lower transistors and generate the upper and lower control nodes. Alternately, the gate or base of the upper (lower) transistor is driven by an op amp receiving an upper (lower) bandgap voltage and the upper (lower) control node as negative feedback.