Cascode Chopping Transconductor for Low-Noise Sigma-Delta ADCs
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Solution Overview
Problem
Moderate bandwidth sigma-delta analog-to-digital converters face significant challenges with flicker noise, particularly in CMOS devices of 45 nm and 65 nm sizes, leading to increased device size, current consumption, and parasitic capacitance, as well as quantization noise folding due to conventional chopping techniques.
Innovation Solution
A chopping transconductor configuration that includes a transconductor input stage, a chopping switch, and a cascode transistor, where the switch output is coupled through the cascode transistor to isolate chopping switches from quantization noise, allowing for higher chopping frequencies without increasing power consumption or requiring clock boosters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If device size is increased to reduce flicker noise, then flicker noise is reduced, but device size increases 2 to 4 times and parasitic capacitance increases
Solution Approach 1:
The patent employs chopping switches that periodically switch at a frequency higher than the Nyquist rate (fchop > fclk/2) to modulate the input signal. This periodic switching action transfers the signal to higher frequency bands where flicker noise has less impact, effectively reducing flicker noise without requiring larger device sizes. The chopping frequency is deliberately chosen to be above the Nyquist rate to prevent quantization noise folding while maintaining small device dimensions.
Solution Approach 2:
The patent introduces clock booster circuits as intermediary components that generate boosted clock signals with higher voltage swings. These boosted clocks drive the chopping switches more effectively, reducing switch resistance and improving signal transfer efficiency. This intermediary mechanism enables the chopping switches to operate at higher frequencies with better performance without proportionally increasing power consumption, thus resolving the contradiction between noise reduction and device size.
2Measurement precision
If chopping frequency is increased above Nyquist rate, then quantization noise folding is prevented, but power consumption increases and clock boosters are required
Solution Approach 1:
The patent uses periodic chopping action at frequencies above the Nyquist rate to prevent quantization noise from folding back into the signal band. By switching periodically at fchop > fclk/2, the signal is upconverted to higher frequencies where quantization noise does not alias into the baseband, thereby improving measurement precision without requiring excessive power consumption.
Solution Approach 2:
The patent changes the voltage parameter of the clock signals by introducing clock booster circuits that transform standard clock levels to higher voltage swings. This parameter change enables the chopping switches to operate with lower resistance and better switching performance at high frequencies, achieving improved quantization noise performance while managing power consumption through optimized voltage levels rather than simply increasing current.
3Area of stationary object
If device size is reduced to maintain small ADC, then flicker noise increases, but increasing current consumption is needed to combat parasitic poles
Solution Approach 1:
The patent applies periodic chopping at frequencies above the Nyquist rate to shift the signal spectrum to higher frequencies. This periodic modulation moves the signal away from the low-frequency region where flicker noise dominates, allowing small device sizes to be used without suffering from excessive flicker noise. The chopping frequency is selected to be greater than fclk/2 to ensure that even with small devices, the signal remains in a noise-friendly frequency region.
Solution Approach 2:
The patent introduces clock booster circuits as intermediaries that provide enhanced voltage drive to the chopping switches. This intermediary mechanism compensates for the effects of small device sizes by providing stronger switching action, thereby maintaining signal integrity and reducing the impact of parasitic poles without requiring increased current consumption or larger device dimensions.
4Stability of the object's composition
If current consumption is increased to maintain parasitic poles, then stability is improved, but power consumption increases
Solution Approach 1:
The patent employs periodic chopping action that modulates the signal to higher frequencies, where the impact of parasitic poles is reduced. By operating at chopping frequencies above the Nyquist rate, the signal is transferred to frequency regions where parasitic poles have less detrimental effect on stability, allowing the ADC to maintain stability with lower current consumption than would be required at lower frequencies.
Solution Approach 2:
The patent changes the frequency parameter of signal processing by implementing chopping at frequencies greater than the Nyquist rate. This parameter change shifts the operating frequency away from regions dominated by parasitic poles, thereby maintaining ADC stability without requiring increased current consumption to compensate for parasitic effects. The frequency transformation effectively decouples stability requirements from current consumption requirements.
Data Source
AI summary
A chopping transconductor includes an transconductor input stage coupled with input signals of the chopping transconductor; a chopping switch coupled with an output of the transconductor input stage, the chopping switch having a switch output; and a cascode transistor, wherein the switch output is coupled to an output of the chopping transconductor through the cascode transistor. The chopping transconductor may be used in an analog-to-digital converter to isolate chopping switches from junctions with quantization noise.