Cascode Circuit Tunable Gate-Drain Capacitance
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Solution Overview
Problem
Parasitic capacitances in power transistors lead to reduced efficiency in power circuits due to switching losses, which existing technologies have not adequately addressed.
Innovation Solution
A cascode circuit with a tunable capacitance is designed, comprising a high voltage transistor and a low voltage transistor, where a control pad is used to adjust the equivalent gate-drain capacitance by receiving an adjust signal, allowing for the circuit to be configured for different applications and reducing switching losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If power transistors are used to withstand high voltages and currents, then power supply capability is improved, but parasitic capacitances increase causing higher switching losses
Solution Approach 1:
The power transistor is segmented into two separate transistors: a high-voltage transistor for withstanding high voltages and currents, and a low-voltage transistor for controlling the switching operation. This segmentation allows each transistor to be optimized for its specific function, reducing the parasitic capacitance of the power transistor while maintaining high power supply capability
Solution Approach 2:
The low-voltage transistor acts as an intermediary between the control signal and the high-voltage transistor. It controls the switching of the high-voltage transistor, enabling the high-voltage device to operate with lower parasitic capacitance and reduced switching losses while still being controlled efficiently
2Loss of energy
If parasitic capacitances are reduced to lower switching losses, then energy efficiency is improved, but the ability to withstand high voltages and currents may be compromised
Solution Approach 1:
The power transistor is segmented into two separate transistors: a high-voltage transistor for withstanding high voltages and currents, and a low-voltage transistor for controlling the switching operation. This segmentation allows each transistor to be optimized for its specific function, reducing the parasitic capacitance of the power transistor while maintaining high power supply capability
Solution Approach 2:
The circuit dynamically switches between different transistor configurations during operation. The low-voltage transistor enables the high-voltage transistor to operate in an optimized state with reduced parasitic capacitance during switching operations, while maintaining the ability to withstand high voltages and currents when needed
3Device complexity
If a fixed capacitance design is used, then device complexity is reduced, but adaptability to different applications is limited
Solution Approach 1:
The circuit includes a variable capacitor that can be dynamically adjusted to change the capacitance value. This dynamic adjustment capability allows the cascode circuit to be adapted to different applications and operating conditions without increasing the basic circuit structure complexity
Solution Approach 2:
The capacitance parameter of the circuit can be changed by adjusting the variable capacitor. This allows the same circuit design to be adapted to different applications by simply changing the capacitance value, providing versatility without requiring multiple different circuit designs
Data Source
AI summary
A semiconductor device and a cascode circuit are disclosed herein. The semiconductor device includes a first transistor and a second transistor. The first transistor includes a first electrode, a second electrode, a control electrode, and a control pad. The second transistor includes a first electrode, a second electrode, a control electrode, and a control pad. The second electrode of the first transistor is configured to receive a first predetermined voltage. The control electrode of the first transistor is configured to receive an input signal. The first electrode of the second transistor configured to receive a second predetermined voltage. The second electrode of the second transistor is electrically coupled to the first electrode of the first transistor. The control pad is disposed between the first electrode of the second transistor and the control electrode of the second transistor, and is configured to receive a first adjust signal.