Cascode Delay Cell With Continuous Bias-Controlled Timing
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Solution Overview
Problem
Conventional delay cells require a large circuit area and numerous selection circuits, with delay time limited to a fixed unit of the inverter, restricting their adjustability and efficiency.
Innovation Solution
The proposed delay cell incorporates cascode transistors and inverters, where cascode transistors generate bias currents in response to control voltages, allowing adjustable delay times by varying these voltages, thereby reducing circuit area and enabling continuous delay time adjustment without fixed units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple inverters are connected in series to realize the delay cell, then the delay function is achieved, but the circuit area becomes large and the number of selection circuits increases
Solution Approach 1:
The patent changes the control parameter from discrete inverter switching to continuous bias current control through cascode transistor gate voltages. By adjusting the gate voltages of the cascode transistors, the bias current flowing through the inverter is continuously variable, enabling continuous delay adjustment without changing the inverter structure or adding selection circuits.
2Reliability
If multiple inverters are connected in series to realize the delay cell, then the delay function is achieved, but the number of selection circuits increases
Solution Approach 1:
The patent extracts the delay control function from the inverter chain structure itself and places it in the cascode transistor bias generation stage. By taking out the need for multiple selection circuits and implementing delay control through bias current modulation at the transistor level, the design simplifies the overall circuit architecture while maintaining the delay function.
3Device complexity
If the delay time is limited to a delay time unit of the inverter, then the circuit structure is simple, but the adjustability of delay time is restricted
Solution Approach 1:
The patent introduces dynamic control of the bias current through variable gate voltages on the cascode transistors. This allows the delay time to be dynamically adjusted continuously by changing the control voltages, transforming the static delay determined by inverter chain length into a dynamically可调 parameter without complicating the basic inverter structure.
Data Source
AI summary
A delay cell includes a cascode transistor and an inverter. The cascode transistor is used to receive a control voltage to generate a bias current, and includes a source terminal, a drain terminal, and a gate terminal receiving the control voltage. The inverter is coupled to the cascode transistor and used to generate an output signal according to the bias current in response to an input signal.