Cascode DLVR Cell Layout for Low ON-Resistance Regulation
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Solution Overview
Problem
Current digital low-dropout voltage regulators (DLVRs) face challenges in achieving high current density and low ON-resistance, which are essential for efficient and precise voltage regulation in integrated circuit devices like application processors.
Innovation Solution
The design optimizes DLVRs by appropriately sizing and placing the active region and metal layers within the functional cells of integrated circuit devices, using a cascode configuration of transistors and conductive pillars, and employing a stacked via structure to minimize resistance and enhance electromigration performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DLVR designs are used, then device simplicity is maintained, but current density and ON-resistance performance are insufficient
Solution Approach 1:
The DLVR is divided into multiple functional blocks including a cascode regulator block with stacked transistors, a reference voltage block, and a digital control block. This segmentation allows each block to be optimized independently for its specific function while contributing to overall performance.
Solution Approach 2:
The patent implements a nested structure where the cascode transistors are stacked vertically with multiple metal layers and via structures nested between them. The conductive pillars are nested within the active region, and multiple conductive layers are nested above the active region to create a compact three-dimensional layout that reduces footprint while maintaining performance.
2Reliability
If active region and metal layers are not optimized, then manufacturing is simpler, but ON-resistance is high and current capacity is limited
Solution Approach 1:
The active region is specifically engineered with optimized dimensions and material composition in the region where current density is critical. The conductive layers are strategically positioned and sized to provide low resistance paths exactly where needed for high current flow, while other regions maintain standard fabrication requirements.
Solution Approach 2:
The patent transitions from a two-dimensional planar layout to a three-dimensional structure by stacking multiple metal layers and via structures vertically above the active region. This vertical stacking reduces the lateral footprint while increasing the effective conductive cross-section, thereby improving current density without proportionally increasing manufacturing complexity.
3Reliability
If standard via structures are used, then fabrication is easier, but electromigration performance and resistance are not optimized
Solution Approach 1:
The via structures are formed as composite conductive paths combining multiple materials and layers, including copper or other low-resistance metals in the via plugs, conductive plugs, and interconnect layers. This composite approach reduces overall resistance and improves electromigration performance compared to single-material via structures.
Solution Approach 2:
Multiple via structures are nested vertically to create stacked conductive paths. The vias are positioned to overlap or align across different metal layers, creating a continuous low-resistance pathway from the active region through multiple conductive layers to the output. This nested via arrangement reduces total resistance and distributes current flow to improve electromigration resistance.
4Reliability
If DLVR occupies large area, then performance can be improved, but area efficiency decreases
Solution Approach 1:
The patent utilizes vertical stacking of metal layers and via structures to achieve high performance in a compact footprint. By moving functionality from the lateral plane to the vertical dimension, the DLVR maintains precise voltage regulation capabilities while occupying minimal chip area, achieving excellent area efficiency.
Solution Approach 2:
Multiple functional elements are merged into a compact integrated structure. The cascode transistors, reference voltage circuit, digital control logic, and output stage are combined in a single DLVR cell with shared conductive paths and stacked layouts, reducing the total area required compared to distributed implementations.
Data Source
AI summary
In some embodiments, an integrated circuit device includes multiple rows of functional cells, with each row having a cell height. At least one of rows of functional cells includes at least one digital low-dropout voltage regulator (DLVR) cell with the cell height for the row. The DLVR cell includes: an input terminal, an output terminal, a voltage supply terminal, a reference voltage terminal, and one or more pairs of transistors. Each pair of transistors are arranged in cascode configuration connected between the voltage supply terminal and output terminal. The gate of one of the transistors the cascode configuration is connected to the input terminal, and the gate of the other transistor in the cascode configuration is connected to the reference voltage terminal. The four terminals each comprises a metal track in the bottom metal layer and disposed within the cell height.