Cascode ESD Clamp With RC Delay for Overdrive Leakage Control
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Solution Overview
Problem
In semiconductor manufacturing, the evolution to smaller node sizes (e.g., 5 nm, 4 nm, 3 nm) requires lower maximum applied voltages, leading to reliability issues in advanced transistors when mixed with older 7 nm chips on the same PCB, necessitating an overdriving design that poses challenges for electrostatic discharge clamps.
Innovation Solution
An electrostatic discharge clamp comprising a clamping circuit with transistors in cascode configuration, a capacitor and resistor network for RC delay, and a bias circuit to control the driving circuit, ensuring reliable electrostatic discharging without parasitic leakage paths, using either p-channel or n-channel metal oxide semiconductor field-effect transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If overdriving design is used to support both 7 nm and advanced (5 nm/4 nm/3 nm or below) chips on the same PCB, then power system versatility is improved, but reliability of advanced transistors deteriorates due to high voltage stress
Solution Approach 1:
The patent introduces an electrostatic discharge clamp circuit as an intermediary protective device between the power system and advanced transistors. This clamp circuit selectively activates during electrostatic discharge events to divert harmful current away from vulnerable transistors, thereby protecting reliability while maintaining overdriving capability for power system versatility.
2Reliability
If conventional electrostatic discharge clamp is used in overdriving system, then electrostatic discharge protection is provided, but parasitic leakage paths cause reliability deterioration
Solution Approach 1:
The patent employs dynamic control of the electrostatic discharge clamp circuit through a driving circuit that responds to voltage changes. The clamp transistors are dynamically switched on during electrostatic discharge events and off during normal operation, eliminating static parasitic leakage paths while maintaining protective functionality when needed.
Solution Approach 2:
The patent changes the operational parameters of the clamp circuit by using a bias circuit to control the threshold voltage and operating point of the clamp transistors. This ensures the transistors remain off during normal low-voltage operation (preventing leakage) and turn on rapidly when voltage exceeds the threshold during electrostatic discharge events.
3Speed
If RC delay is introduced to control driving circuit turn-on, then electrostatic discharge response time is improved, but device complexity increases due to additional capacitor and resistor network
Solution Approach 1:
The patent merges the RC delay network with the existing bias circuitry of the electrostatic discharge clamp. The capacitors and resistors are integrated into the control path of the clamp transistors, sharing common nodes and signals with the bias circuit, thereby achieving rapid response without proportionally increasing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses leakage current and ensures reliable electrostatic discharge management in overdriving systems by introducing an RC delay and biasing the transistors appropriately, maintaining low turn-on voltage for efficient discharging.
Implementation Method 1
The capacitor and resistor network introduces an RC delay in response to an electrostatic discharge event to control the driving circuit to turn on the transistors of the clamping circuit for electrostatic discharging.
Implementation Method 2
An electrostatic discharge clamp is a necessary device in a chip. An electrostatic discharge clamp having high reliability in an overdriving system is called for.
Data Source
AI summary
An electrostatic discharge clamp is shown, which includes a clamping circuit, a driving circuit, a capacitor and resistor network, and a bias circuit. The clamping circuit has a plurality of transistors connected in a cascode configuration. The driving circuit is coupled to the gates of the transistors of the clamping circuit. The capacitor and resistor network introduces an RC delay in response to an electrostatic discharge event to control the driving circuit to turn on the transistors of the clamping circuit for electrostatic discharging. The bias circuit biases the driving circuit to turn off the transistors of the clamping circuit when the capacitor and resistor network does not detect the electrostatic discharge event.