GaN HEMT FPGA Inverter Structure for Power Loss and Heat Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Field-programmable gate arrays (FPGAs) used in artificial intelligence accelerators for autonomous driving consume high power, reducing the range of electric vehicles and generating excessive heat due to their complex logical structures and wiring, which is not efficiently managed by conventional Si transistors.
Innovation Solution
The use of high-electron-mobility transistors (HEMTs) with a GaN and AlGaN layer structure in the FPGA device, specifically in a cascode inverter configuration, along with a Si substrate, to minimize energy loss and heat production, and integration of components like parallel shift registers and programmable I/O blocks on the same substrate for miniaturization and reduced material usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional Si transistors are used in FPGA devices for autonomous driving calculations, then the device can perform required computational functions, but power consumption increases and thermal losses increase
Solution Approach 1:
The patent changes the material parameter of the transistor from conventional silicon to GaN-based HEMT technology. This fundamental material parameter change enables lower power consumption and reduced thermal losses while maintaining the required computational functionality for autonomous driving calculations in FPGA devices
Solution Approach 2:
The patent employs composite material structure by integrating GaN and AlGaN layers to form HEMT devices within the FPGA architecture. This composite semiconductor structure leverages the superior electrical and thermal properties of nitride materials to achieve both low power consumption and effective thermal management
2Adaptability or versatility
If FPGAs are used in AI accelerators for autonomous driving, then flexibility and functionality are improved, but power consumption increases by 1-5 kW
Solution Approach 1:
The patent applies parameter change by transitioning from conventional silicon transistor technology to GaN-based HEMT technology in FPGA devices. This enables AI accelerators to maintain their functional flexibility and adaptability for autonomous driving applications while dramatically reducing power consumption from the typical 1-5 kW range
3Productivity
If more logical gates and wiring are added to FPGAs to increase computational capacity, then processing power is improved, but power consumption increases
Solution Approach 1:
The patent changes the fundamental material parameter of the transistor technology from silicon to GaN-based HEMT. This enables the FPGA to achieve higher computational capacity with more logical gates and wiring while consuming less power, as the nitride-based transistors inherently operate with lower power requirements
Solution Approach 2:
The patent converts the typically harmful effect of increased wiring and logical gates (which normally leads to higher power consumption) into a benefit. By using GaN-based HEMT technology, the additional computational elements can be added without the usual power penalty, and the lower operating temperature actually enables more gates to be integrated efficiently
4Ease of manufacture
If conventional Si transistors are used in FPGAs, then manufacturing is straightforward, but thermal runway effects occur due to current leakage
Solution Approach 1:
The patent employs composite semiconductor materials by integrating GaN and AlGaN layers to form HEMT devices. This composite structure provides superior thermal stability and eliminates the thermal runaway effects seen in conventional silicon transistors, while the manufacturing process has been adapted to incorporate these nitride-based materials into FPGA fabrication
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances energy efficiency, reduces power consumption, and minimizes waste heat, thereby improving the operational range of electric vehicles and reducing thermal management needs, while maintaining high voltage/current operation and switching frequencies.
Implementation Method 1
The logic inverter comprises at least one high-electron-mobility transistor, HEMT. Each HEMT comprises an AlyGay-1N layer structure
Implementation Method 2
The HEMT comprises an AlyGay-1N layer structure, wherein 0≤x<1, enabling substantially two-dimensional electron transport. This interface may be understood to enable the forming of a so-called two-dimensional electron gas, 2DEG
Implementation Method 3
Nitride HEMTs, e.g. HEMTs comprising a GaN and AlGaN layer structure interface generally provide higher voltage/current operation, higher switching frequencies, and less energy loss
Implementation Method 4
The use of a cascode inverter setup may provide greater isolation of the inverter input and output signals by reducing reverse transmission of current as there is no direct coupling from the output node to the input node. Furthermore, the negative consequences of the Miller effect, such as e.g. an increase of the input capacitance, may be mitigated
Data Source
AI summary
There is provided a field-programmable gate array, FPGA, device (100) comprising a configurable logic block, CLB, (110) comprising a logic inverter (120) comprising a high-electron-mobility transistor, HEMT, (130), wherein the HEMT comprises: a Si substrate (384); an AlyGay-1N layer structure (380), wherein 0<y≤1; a GaN layer structure (382); and a crystal transition layer structure (386) arranged on the Si substrate. The crystal transition layer comprises: a plurality of vertical nanowire structures (388) perpendicularly arranged on the Si substrate, and an AlxGax-1N layer structure (389), wherein 0≤x<1, wherein the AlxGax-1N layer structure is arranged to vertically and laterally enclose the vertical nanowire structures. There is also provided an AI processing system comprising said FPGA device (100).


