Cascode-Free Level Shifter for Power-Up Leakage Blocking
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Solution Overview
Problem
Existing level shifting circuits in integrated circuits face challenges during power-up sequences due to leakage currents, which are not effectively managed, leading to silicon breakdown and increased power consumption, especially as fabrication processes advance to nano scales and multiple power domains are integrated into a single chip.
Innovation Solution
A cascode-free level shifting circuit using cross-coupled logic with enable signal-controlled NMOS transistors to control leakage current, eliminating the need for additional power domains and start-up signals, and incorporating NOR logic to block leakage currents independently of power-up sequence timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional level shifters are used during power-up sequence, then leakage current flows from VDDH to ground, but adding cascode transistors to block leakage increases device complexity and area
Solution Approach 1:
The patent applies preliminary action by generating the enable signal before the power-up sequence begins. The enable signal is prepared in advance to control the NMOS transistors, preventing leakage current from flowing during the power-up transition. This proactive approach blocks leakage before it can occur, eliminating the need for complex cascode structures while maintaining energy efficiency.
2Loss of energy
If cascode transistors are added to block leakage current, then leakage is reduced, but operating speed decreases due to additional resistance and capacitance
Solution Approach 1:
The enable signal is generated in advance and used to control NMOS transistors that block leakage current during the power-up sequence. This approach prevents leakage without introducing the resistance and capacitance penalties associated with cascode transistors, thereby maintaining high operating speed while reducing energy loss.
3Loss of energy
If enable signal is added to control leakage, then leakage current is blocked, but device complexity increases due to additional control signals
Solution Approach 1:
The enable signal serves multiple functions: it controls the NMOS transistors to block leakage current during power-up, and it coordinates with the cross-coupled logic to ensure proper level shifting operation. This multi-functional approach blocks leakage without requiring separate dedicated control circuits, maintaining simplicity while achieving energy efficiency.
4Loss of energy
If VDDL leads VDDH in power-up sequence, then leakage is blocked, but this creates a system design restriction on power sequencing
Solution Approach 1:
The enable signal acts as an intermediary that decouples the leakage blocking function from the power sequence timing. By using the enable signal to control NMOS transistors, the circuit can block leakage current regardless of whether VDDL or VDDH rises first. This eliminates the design restriction while maintaining energy efficiency, providing flexibility in power domain sequencing.
Data Source
AI summary
Level shifting circuitry and corresponding enable signal generating circuitry provides improved leakage current control while eliminating the need for supplying reference voltage input in the enable signal generator. The level shifting circuitry is a type of cascode free level shifting circuit that does not include cascode transistors as in the prior art but instead utilizes cross coupled logic to provide level shifting while also utilizing enable signal controlled transistors to control leakage current through the cross coupled logic during power up sequencing. The level shifting circuitry provides improved leakage current limiting structure for power up sequencing whether a lower level supply voltage ramps up faster than the higher level supply voltage or vice a versa.