Cascode Amplifier Gain Switching with Selective Parallel Biasing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing cascode amplifier circuits face challenges in achieving both low noise performance and high linearity, especially when gain is switched in response to varying signal strengths, as they either compromise on noise or linearity.
Innovation Solution
A cascode amplifier circuit with a first transistor circuit comprising multiple parallel transistors, a load circuit, and a bias circuit that selectively supplies bias voltage to adjust the effective transistor size, allowing for high gain and linearity by switching between 'gain importance mode' and 'linearity importance mode' without adding parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a bias state of a first-stage FET is arranged constantly, then the amplifier circuit structure is simple, but high linearity cannot be achieved when gain is reduced and low noise performance cannot be achieved when gain is increased
Solution Approach 1:
The patent applies dynamics by making the bias state of the first-stage FET changeable rather than constant. A bias control circuit dynamically adjusts the bias voltage applied to the gate of the first-stage FET based on the required gain level, enabling the amplifier to switch between different operating states (high gain/low noise mode and low gain/high linearity mode), thus resolving the contradiction between structural simplicity and gain switching capability.
2Power
If multiple transistors are connected in parallel to increase gain, then gain is improved, but parasitic capacitance increases and noise performance deteriorates
Solution Approach 1:
The patent applies parameter changes by controlling the operating state (on/off) of individual transistors in the parallel configuration rather than keeping all transistors constantly active. The bias control circuit selectively activates only the necessary number of transistors based on the required gain level, thereby maintaining high gain when needed while minimizing parasitic capacitance by keeping other transistors in the off state, thus preventing noise performance deterioration.
3Object-affected harmful factors
If transistors are selectively turned off to reduce parasitic capacitance, then noise performance is improved, but gain is reduced
Solution Approach 1:
The patent resolves this contradiction through dynamic control of transistor switching states. The bias control circuit continuously monitors the required gain level and dynamically adjusts which transistors are active, enabling the system to achieve optimal balance between parasitic capacitance reduction and gain maintenance based on real-time operational requirements.
Solution Approach 2:
The patent changes the operating parameters of the transistors by selectively adjusting their bias states between on and off conditions. This parameter change allows the amplifier to adapt its effective transistor count and corresponding parasitic capacitance levels while maintaining the required gain through intelligent selection of active devices.
Data Source
AI summary
An amplifier circuit is a cascade amplifier circuit that includes a first transistor circuit including a signal input portion to which a signal is input from outside; a load circuit connected between the first transistor circuit and a power-supply line; and a second transistor cascode-connected between the load circuit and the first transistor circuit. The first transistor circuit is constituted by a plurality of transistors connected in parallel, and a bias circuit is provided that selectively supplies a bias voltage to the plurality of transistors.