Cascode GaN FET with Active Clamp for Leakage Current Management
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Solution Overview
Problem
Gallium Nitride (GaN) based field effect transistors, used in high voltage applications, are typically 'normally on' devices, requiring a negative gate voltage to switch off, which poses challenges in isolating input voltage, leading to potential damage to lower power components and increased risk of avalanche conditions due to high leakage currents.
Innovation Solution
A cascode configuration is employed with a low voltage FET in the source of a high voltage FET, incorporating additional drain-to-source resistance in parallel to manage leakage currents and prevent avalanche, using a resistive divider with a common node connected to the gate of a third FET for active clamping, ensuring stable operation and preventing power loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a cascode configuration is used with a low voltage FET in the source of a high voltage FET, then the device can be switched off by turning off the low voltage FET, but the drain-source voltage of the low voltage FET increases due to leakage currents, leading to avalanche conditions
Solution Approach 1:
The patent applies preliminary anti-action by introducing a clamp circuit that preemptively counteracts the harmful voltage increase caused by leakage currents. The clamp circuit is designed to activate when the drain-source voltage of the low voltage FET reaches a predetermined threshold, applying a counteracting effect that prevents the voltage from rising further and avoiding avalanche conditions before they can occur.
Solution Approach 2:
The clamp circuit serves as an intermediary element between the low voltage FET and the high voltage FET. It mediates the harmful interaction by detecting when the drain-source voltage becomes excessive and intervening to clamp it at a safe level, thus protecting the low voltage FET from avalanche damage while maintaining the cascode switching functionality.
2Reliability
If additional resistance is added in parallel to manage leakage currents, then avalanche conditions are prevented, but device complexity increases
Solution Approach 1:
The patent merges the clamp circuit functionality with the existing cascode structure by integrating it into the same device. The clamp circuit shares common elements with the cascode configuration, such as the low voltage FET and associated capacitors, thereby achieving avalanche prevention without proportionally increasing device complexity. The shared components reduce the overall component count compared to a fully separate implementation.
Solution Approach 2:
The low voltage FET serves multiple functions: it acts as the switching element in the cascode configuration and simultaneously serves as part of the clamp circuit when activated. This multi-functionality reduces the need for separate dedicated components for each function, thereby limiting the increase in device complexity while achieving both switching control and avalanche prevention.
3Power
If GaN HEMT or JFET devices are used for high voltage operation, then high power and high efficiency are achieved, but the input supply voltage cannot be isolated, increasing risk to lower power circuits
Solution Approach 1:
The patent segments the high voltage power switching function from the low voltage control function using the cascode configuration. The high voltage FET handles the power switching while the low voltage FET provides control and isolation. This segmentation allows the system to achieve high power operation while protecting lower power circuits through the inherent voltage isolation provided by the low voltage FET's off-state blocking capability.
Solution Approach 2:
The low voltage FET acts as an intermediary that isolates the high voltage input from lower power control circuits. When the low voltage FET is turned off, it blocks the high voltage from reaching sensitive control circuits and ancillary components, thereby providing the necessary voltage isolation while allowing the high voltage FET to operate at full power capability.
Data Source
AI summary
A semiconductor device, comprising first and second field effect transistors arranged in a cascode configuration: wherein the first field effect transistor is a depletion mode transistor; and wherein the second field effect transistor comprises a first source to gate capacitance and a second additional source to gate capacitance connected in parallel to the first source to gate capacitance. A power factor correction (PFC) circuit comprising the semiconductor device. A power supply comprising the PFC circuit.