Cascode GaN FET Circuit for Reverse Recovery and EMC
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Solution Overview
Problem
Conventional semiconductor devices with cascode connections face challenges in achieving good reverse recovery characteristics and electromagnetic compatibility (EMC) without increasing manufacturing costs, often requiring negative power sources and trade-offs between reverse recovery and EMC performance.
Innovation Solution
Incorporating a diode and/or capacitor in the cascode connection of normally-on and normally-off field-effect transistors, allowing gate drive current to flow through these components during turn-off, which enhances switching speed and reduces reverse recovery time without the need for negative power sources or excessive resistance reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a normally-on type GaN FET is used, then high withstand voltage, high-speed operation, high heat-resistance, and low on-resistance are achieved, but a negative voltage supply source is required which increases cost and circuit size
Solution Approach 1:
The patent extracts the negative voltage supply requirement by using a normally-off type MOSFET in a cascode configuration with the normally-on type GaN FET. The MOSFET's body diode and gate structure enable the GaN FET to operate without an external negative voltage source, eliminating the problematic component while preserving the desired device properties.
Solution Approach 2:
The normally-off type MOSFET serves multiple functions: it provides the necessary voltage level shifting, acts as a protection element through its body diode, and enables the GaN FET to operate in a normally-off mode without requiring a dedicated negative voltage supply circuit. This multi-functionality resolves the contradiction between performance and circuit complexity.
2Device complexity
If cascode connection is used to achieve normally-off operation, then negative voltage supply is eliminated, but reverse recovery current becomes large which deteriorates EMC
Solution Approach 1:
The patent optimizes the gate resistance value in the cascode configuration to control the turn-off characteristics of the MOSFET. By carefully selecting the gate resistance, the reverse recovery current is minimized while maintaining proper switching operation. This parameter optimization resolves the contradiction between eliminating negative voltage supply and controlling reverse recovery current.
3Speed
If resistance is reduced to improve reverse recovery characteristic, then switching speed increases, but dv/dt increases which deteriorates EMC
Solution Approach 1:
The patent optimizes the gate resistance value to achieve a balance between switching speed and dv/dt control. By selecting an appropriate resistance value, the gate charging and discharging rates are controlled to provide fast switching while limiting the voltage change rate that causes electromagnetic interference. This resolves the contradiction between switching speed and noise generation.
Data Source
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AI summary
A semiconductor device including: an FET; a MOSFET having a drain thereof connected with a source of the FET; a resistor having one end thereof connected with a gate of the FET and having the other end thereof connected with a source of the MOSFET; and a diode having an anode thereof connected with the gate of the FET and having a cathode thereof connected with the source of the MOSFET.