Cascode GaN-MOSFET Package Layout for Low Parasitic Switching
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Solution Overview
Problem
Existing semiconductor devices with GaN HEMTs in parallel layout face challenges in achieving stable performance due to high package resistance and parasitic inductances, making it difficult to maintain consistent operation and power density.
Innovation Solution
A semiconductor device comprising a MOSFET die and two GaN dies arranged in a cascode configuration, where the first GaN die is in a normal orientation and the second GaN die is inverted, with a clip-bonded design that connects the gates and drain-source terminals to improve stability and reduce package resistance, and a method of manufacturing involving specific adhesive and clip attachment steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If GaN HEMTs are arranged in parallel layout, then power density is increased, but package resistance and parasitic inductances increase causing unstable performance
Solution Approach 1:
The patent transitions from a planar parallel layout to a three-dimensional stacked configuration where GaN HEMT dies are vertically arranged on top of each other. This vertical stacking approach increases power density while reducing the horizontal footprint and minimizing parasitic inductances associated with lateral connections, thereby resolving the contradiction between power density and performance stability.
Solution Approach 2:
The patent implements a nested structure where multiple GaN HEMT dies are stacked vertically, with each die nested within the same package footprint. The MOSFET die controls multiple GaN dies in a cascode arrangement, creating a compact nested configuration that achieves high power density without increasing package resistance or parasitic inductances.
2Power
If GaN HEMTs are arranged in parallel layout, then power switching capability is enhanced, but package resistance increases
Solution Approach 1:
By stacking GaN HEMT dies vertically in three dimensions rather than arranging them horizontally in parallel, the patent reduces the length of interconnect paths and minimizes package resistance while maintaining enhanced power switching capability through the stacked configuration.
Solution Approach 2:
The patent divides the power switching function across multiple segmented GaN HEMT dies stacked vertically, with each die contributing to the overall power capability. This segmentation allows for shorter individual connection paths within each die, reducing cumulative package resistance while maintaining total power switching capability.
3Power
If GaN HEMTs are arranged in parallel layout, then current handling is improved, but parasitic inductances increase causing unstable operation
Solution Approach 1:
The vertical stacking architecture reduces the loop area for current paths by confining them in the vertical dimension rather than allowing large horizontal loops. This minimizes parasitic inductances generated by the package layout while maintaining high current handling capability through the stacked GaN HEMT dies.
Data Source
AI summary
A semiconductor device is provided, including a MOSFET die, a first GaN die and a second GaN die. The first GaN die and the second GaN die are arranged in a cascode arrangement. The second GaN die is positioned in an inverted orientation. The MOSFET die controls the first GaN die and the second GaN die.