Cascode Switching Power Supply Gate Control During Dead Time
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Solution Overview
Problem
The use of cascode transistors in switching power supply circuits leads to excessive gate-source and gate-drain voltages in power transistors, causing breakdown and damage due to charge discharge through body diodes during dead times, reducing the reliability of the circuit.
Innovation Solution
A switching power supply circuit design that includes a control circuit and transistors to manage gate potentials within safe voltage limits, using transistors N1 and N2 to maintain a gate-drain voltage of power transistors below their threshold, and additional transistors N3 and N4 to quickly discharge charges, preventing excessive voltages and ensuring reliable operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If cascode transistors are used as power transistors in the switching power supply circuit, then power consumption is reduced and power conversion efficiency is improved, but gate-source voltage and gate-drain voltage become excessively high during dead time, causing transistor breakdown and reduced reliability
Solution Approach 1:
The patent introduces a control circuit as an intermediary between the switching signal and the power transistors. This control circuit actively manages the gate voltages of the power transistors during dead time, preventing excessive voltage buildup that would otherwise cause breakdown. The control circuit mediates the conflict between using cascode transistors for low power consumption and maintaining transistor reliability by actively regulating voltages during switching transitions.
Solution Approach 2:
The control circuit performs preliminary action by pre-charging or pre-discharging the gate voltages of the power transistors before the actual switching event occurs. During dead time, the control circuit proactively adjusts the gate potentials to prevent excessive voltage accumulation, ensuring that when the next switching cycle begins, the transistors are already in a safe voltage state, thus preventing breakdown before it can occur.
2Power
If multiple lower power transistors are connected in series between the output node and ground, then power handling capability is improved, but voltage distribution becomes unbalanced during dead time, causing some transistors to exceed withstand voltage limits
Solution Approach 1:
The control circuit implements feedback by continuously monitoring the state of the power transistors and adjusting their gate voltages accordingly. During dead time, the control circuit detects which transistors are at risk of exceeding voltage limits and applies corrective voltage adjustments to maintain balanced voltage distribution across all series-connected transistors, ensuring none exceed their withstand voltage limits while maintaining the series configuration for enhanced power handling.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting the gate-source and gate-drain voltages of the power transistors based on their operating state. During dead time, the control circuit modifies these voltage parameters to prevent excessive voltage accumulation on any single transistor, thereby maintaining reliable operation of the series-connected transistor string while preserving the power handling benefits of the series configuration.
Data Source
Figure 1A
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AI summary
Embodiments of this application provide a switching power supply circuit and an electronic device. The switching power supply circuit includes: a power transistor circuit, including a plurality of power transistors coupled in series between a power supply end and a ground, where a first electrode of a first power transistor in the plurality of power transistors is coupled to the power supply end by using a second power transistor in the plurality of power transistors, and a second electrode of the first power transistor is coupled to the ground by using a third power transistor in the plurality of power transistors; a drive circuit, configured to: receive a pulse width modulation PWM signal, generate a drive signal based on the PWM signal to drive the second power transistor and the third power transistor, and maintain a gate of the first power transistor at a preset voltage; a first transistor, where both a gate and a first electrode of the first transistor are coupled to a gate of the third power transistor, and a second electrode of the first transistor is coupled to the ground by using a first switch; and a control circuit, configured to: receive the PWM signal, and generate a first control signal based on the PWM signal to control the first switch. This can improve reliability of the switching power supply circuit.