Cascode Power Amplifier Gate Control for Lower Voltage Stress
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Solution Overview
Problem
Driving GaN power transistors in switch-mode power amplifiers requires high voltage swing and negative biasing, necessitating the use of high-breakdown voltage transistors, which are costly and complex to implement.
Innovation Solution
A power amplifier circuit using two drive circuits with synchronized two-level gate control signals, allowing the use of low-breakdown voltage transistors by reducing voltage stress on the cascode transistor, enabling the use of CMOS technology instead of high-breakdown transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-breakdown voltage transistors are used to drive GaN power transistors, then the transistor can withstand the required voltage swing and negative biasing, but the cost and implementation complexity increase significantly
Solution Approach 1:
The patent divides the single high-voltage transistor function into two separate transistors operating in a cascode configuration. The first transistor handles the high-voltage switching function while the second transistor manages the gate drive signals, allowing each transistor to operate within its optimal voltage range and eliminating the need for a single high-breakdown voltage transistor
Solution Approach 2:
The second transistor acts as an intermediary between the control circuitry and the first transistor. It translates control signals into appropriate gate drive signals for the first transistor, thereby protecting the control circuitry from high voltage stress while enabling proper operation of the power transistor
2Reliability
If high-breakdown voltage transistors are used, then proper GaN transistor operation is achieved, but the cost increases due to special dedicated technologies
Solution Approach 1:
The patent changes the voltage parameters experienced by each transistor in the cascode pair. By properly biasing and controlling the second transistor, the voltage stress on each device is reduced to levels that can be handled by standard, lower-cost transistor technologies rather than requiring expensive high-breakdown voltage devices
3Strength
If synchronized two-level gate control signals are applied to both transistors, then voltage stress on individual transistors is reduced, but the drive circuit complexity increases
Solution Approach 1:
The patent employs dynamic control of the gate signals to both transistors, where the timing and voltage levels of the gate signals are continuously adjusted during operation. This dynamic signaling approach optimizes the voltage distribution across the cascode pair during switching transitions, reducing peak voltage stress on individual devices
Solution Approach 2:
The synchronized two-level gate control signals operate in a periodic manner during switching cycles, with coordinated transitions that regularly reduce voltage stress on the transistors. This periodic control pattern ensures that high voltage stress conditions are avoided while maintaining efficient power transistor operation
Data Source
AI summary
A power amplifier circuit uses an output transistor and a cascode transistor. First and second drive circuits apply gate control signals to the two transistors, which rise and fall in synchronism, and this is such that the voltage drop across the cascode transistor is reduced (compared to a constant gate voltage being applied to the output transistor).