Cascode Transmission Gate Protection for I/O Pad Overvoltage
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Solution Overview
Problem
Integrated circuit devices face challenges in protecting circuitry from charge injection and over/under voltage conditions due to increasing voltage requirements at I/O pads, which exceed the voltage support capabilities of transmission gates, particularly in process nodes below 10 nm.
Innovation Solution
A transmission gate structure with overvoltage and charge injection protection circuitry using a cascode structure and mid-node transistor, employing additional control signals to enable/disable cascode switches and track I/O pad voltage, ensuring safe operating conditions for mid-node transistors by preventing voltage levels outside a safe range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If transmission gates are used in process nodes below 10 nm, then device scaling and integration density are improved, but the circuitry becomes vulnerable to charge injection and overvoltage damage
Solution Approach 1:
A cascode transmission gate structure is introduced as an intermediary between the I/O pad and the mid-node transistor. The cascode structure includes a first transmission gate connected to the I/O pad and a second transmission gate connected to the mid-node transistor, with a cascode node between them. This intermediary structure prevents direct exposure of the mid-node transistor to high voltages and charge injection from the I/O pad, while still enabling signal transmission. The cascode node is held at a safe voltage level through a voltage generation circuit, acting as a protective buffer.
Solution Approach 2:
The voltage generation circuit proactively establishes a safe operating voltage at the cascode node before any overvoltage or charge injection events occur. By pre-configuring the cascode structure with appropriate voltage levels and protection circuitry, the system prepares a cushion against potential damage. The control logic monitors I/O pad voltage and preemptively adjusts the cascode gate voltages to prevent harmful conditions before they can affect the mid-node transistor.
2Adaptability or versatility
If I/O pads operate at higher voltages (e.g., 1.8V), then interface compatibility and voltage support are improved, but transmission gate transistors may be damaged due to exceeding their voltage limits
Solution Approach 1:
The transmission gate is segmented into two separate transmission gates (first and second) connected in series through the cascode node. The first transmission gate handles the high-voltage I/O pad interface, while the second transmission gate operates at lower, safe voltages near the mid-node transistor. This segmentation allows each segment to operate within its safe voltage range while collectively supporting high-voltage I/O operations. The cascode node voltage is independently controlled to ensure it remains within safe limits regardless of I/O pad voltage fluctuations.
3Reliability
If cascode switches are added for protection, then transistor safety is improved, but device complexity increases
Solution Approach 1:
The cascode transmission gate structure serves multiple functions simultaneously: it enables high-voltage I/O interface compatibility, protects the mid-node transistor from overvoltage and charge injection, maintains safe operating voltages through the voltage generation circuit, and provides controlled signal transmission. By integrating these multiple protection and interface functions into a single unified structure, the design achieves comprehensive protection without proportionally increasing complexity. The control logic also manages multiple functions (voltage tracking, gate control, protection) within a unified control framework.
Data Source
AI summary
A transmission gate includes a first P-type transistor and a second P-type transistor coupled in series between a first signal node and an internal node. The transmission gate is enabled by turning on the first P-type transistor and the second P-type transistor to communicate signals between the first signal node and the internal node. The transmission gate is disabled by turning off the first P-type transistor and the second P-type transistor to stop communicating signals between the first signal node and the internal node. While the transmission gate is disabled, a third P-type transistor having a first current electrode coupled to a circuit node between the first and second P-type transistors and a control electrode coupled to the first signal node is used to track voltage of the first signal node and, in response to the tracking, control a voltage level at the circuit node to limit a gate-to-source voltage of the first P-type transistor.