Cascode FET Gate Resistor for Linear Gain Boosting

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing single stage cascode FET amplifiers struggle to provide higher gains at higher frequencies without degrading current drain and linearity, particularly in low noise amplification applications such as those required by 5G communication systems.

Innovation Solution

A gain boosting resistor is coupled in series with the gate capacitor of a cascode transistor to transform the source impedance from capacitive to inductive, creating resonance with the capacitive output impedance of the input transistor, thereby boosting gain without significant noise figure degradation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If the gate capacitor is sized to provide a short at operating frequencies, then gain is improved, but noise figure degrades

Engineering Contradiction:
ImprovegainVSAvoidnoise figure
Core Design Contradiction:
PowerVSObject-affected harmful factors

Solution Approach 1:

The patent changes the impedance parameter of the gate capacitor from purely capacitive (short circuit) to a complex value with both resistive and capacitive components. By selecting a capacitor with equivalent series resistance (ESR) in a specific range (0.1Ω to 10Ω), the gate impedance is transformed to provide gain boost while minimizing noise figure degradation through optimal parameter selection.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The gate capacitor acts as an intermediary element between the cascode transistor gate and ground. Instead of being a simple short circuit, it provides a controlled impedance path that mediates between the need for high gain (short circuit behavior) and low noise figure (open circuit behavior), achieving both objectives through its specific ESR value.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Power

If multiple cascode stages are used to increase gain, then gain is improved, but current drain increases

Engineering Contradiction:
ImprovegainVSAvoidcurrent drain
Core Design Contradiction:
PowerVSUse of energy by moving object

Solution Approach 1:

The patent segments the gain enhancement function between two elements: the cascode transistor configuration and the gate capacitor with ESR. This allows a single cascode stage to achieve the same gain as multiple stages would provide, eliminating the need for additional transistor stages and their associated current drain.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

By changing the impedance parameter of the gate capacitor to include a specific ESR range, the patent enables a single cascode stage to provide enhanced gain without requiring multiple stages, thereby reducing the total current drain while maintaining or improving gain performance.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If the gate capacitor impedance is increased to protect transistors from overvoltage, then transistor reliability is improved, but gain decreases

Engineering Contradiction:
Improvetransistor protectionVSAvoidgain
Core Design Contradiction:
ReliabilityVSPower

Solution Approach 1:

The patent identifies and exploits the ESR parameter of the gate capacitor as a controllable variable. By selecting capacitors with ESR in the range of 0.1Ω to 10Ω, it achieves an optimal balance where the capacitor provides sufficient impedance for transistor protection while maintaining low enough impedance to preserve gain performance.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The gate capacitor with specific ESR serves as an intermediary that simultaneously provides both protection and gain. It mediates between the conflicting requirements of high impedance for protection and low impedance for gain, achieving both functions through its unique impedance characteristics.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method achieves a gain boost of up to 2.9 dB at frequencies between 4.6 GHz and 5.0 GHz with minimal noise figure increase of 0.11 dB, suitable for low noise amplification applications like 5G receive paths.

Implementation Method 1

transform the source impedance from capacitive to inductive, creating resonance with the capacitive output impedance of the input transistor

Methodology Applied
Scientific EffectResonance: Resonance

Data Source

PatentUS12489403B2Cascode gain boosting and linear gain control using gate resistor
Publication Date: 2025.12.02 PSEMI CORP
  • US12489403B2 patent drawing
  • US12489403B2 patent drawing
  • US12489403B2 patent drawing

AI summary

Methods and apparatuses for controlling gain of a single stage cascode FET amplifier are presented. According to one aspect, a series-connected resistor and capacitor is coupled to a gate of a cascode FET transistor of the amplifier, the capacitor providing a short at frequencies of operation of the amplifier. According to another aspect, values of the resistor can be used to control gain of the amplifier. According to yet another aspect, the resistor is a variable resistor whose value can be controlled/adjusted to provide different gains of the amplifier according to a linear function of the resistor value. An input matching network coupled to an input of the amplifier can be used to compensate for different noise figure degradations from different values of the resistor.