Cascode FET Amplifier Gate Resistor for Linear Gain Boosting
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing single stage cascode FET amplifiers face challenges in achieving higher gains at higher frequencies without degrading current drain and linearity, particularly in low noise amplification applications such as 5G communication systems.
Innovation Solution
A single stage cascode FET amplifier is enhanced by coupling a gain boosting resistor in series with a gate capacitor, transforming the source impedance from capacitive to inductive, which generates resonance with the capacitive output impedance of the input transistor, thereby boosting gain without significant noise figure degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple cascode stages or cascaded amplifiers are used to increase gain, then gain is improved, but current drain increases and linearity degrades
Solution Approach 1:
The patent changes the impedance parameter of the cascode transistor source by introducing a series RC network. The resistor transforms the capacitive source impedance to inductive, creating resonance with the input transistor's capacitive output impedance. This parameter transformation enables gain boosting in a single stage without requiring additional amplifier stages, thereby avoiding increased current drain.
2Power
If multiple cascode stages or cascaded amplifiers are used to increase gain, then gain is improved, but linearity degrades
Solution Approach 1:
The patent transforms the source impedance parameter of the cascode transistor from capacitive to inductive using a series RC network. This creates a resonant condition with the input transistor's capacitive output impedance, boosting gain while maintaining the single-stage architecture. The single-stage design with optimized impedance parameters preserves linearity that would otherwise degrade in multi-stage configurations.
3Reliability
If a gate capacitor is sized to provide a short at operating frequencies, then noise figure is improved, but gain is limited
Solution Approach 1:
The patent modifies the gate capacitor configuration by adding a series resistor to create an RC network. This transforms the source impedance from purely capacitive to inductive, enabling resonance with the input transistor's capacitive output impedance. The gate capacitor remains sized to provide a short at operating frequencies for low noise figure, while the series resistor provides the impedance transformation needed for gain boosting.
Solution Approach 2:
The series resistor acts as an intermediary element between the gate capacitor and ground. It transforms the capacitive source impedance to inductive, mediating the interaction between the gate capacitor and the input transistor's output impedance. This intermediary enables the resonant condition that boosts gain without compromising the noise figure performance provided by the gate capacitor.
4Power
If the source impedance of the cascode transistor is capacitive, then the amplifier operates normally, but gain is limited
Solution Approach 1:
The patent changes the source impedance parameter from capacitive to inductive by introducing a series RC network at the cascode transistor gate. The resistor transforms the impedance character, creating an inductive source impedance that resonates with the capacitive output impedance of the input transistor. This parameter transformation enables gain boosting while the gate capacitor maintains low noise figure performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a gain boost of up to 2.9 dB at frequencies from 4 to 5 GHz with minimal noise figure increase, suitable for low noise amplification applications like 5G systems, maintaining linearity and reducing current drain.
Implementation Method 1
generating a resonance between a capacitive impedance at a drain of the input transistor and the inductive source impedance of the output transistor at a frequency of operation of the LNA
Data Source
AI summary
Methods and apparatuses for controlling gain of a single stage cascode FET amplifier are presented. According to one aspect, a series-connected resistor and capacitor is coupled to a gate of a cascode FET transistor of the amplifier, the capacitor providing a short at frequencies of operation of the amplifier. According to another aspect, values of the resistor can be used to control gain of the amplifier. According to yet another aspect, the resistor is a variable resistor whose value can be controlled/adjusted to provide different gains of the amplifier according to a linear function of the resistor value. An input matching network coupled to an input of the amplifier can be used to compensate for different noise figure degradations from different values of the resistor.