Cascode HEMT Structure for Low Off-State Leakage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing HEMT structures face reliability issues due to high leakage current in the off-state, which can lead to degradation over time.
Innovation Solution
A cascode HEMT structure is designed with a depletion-mode transistor and an enhancement-mode transistor connected in series, utilizing a bleed resistor and gate driver to limit the drain-source current to 20 nA/mm in the off-state, ensuring low leakage current and improved reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a depletion-mode transistor is used in HEMT structure, then high-speed performance and low resistance are improved, but high leakage current in off-state occurs
Solution Approach 1:
The HEMT structure is segmented into two transistors: a depletion-mode transistor for high-speed performance and an enhancement-mode transistor for low leakage control. This segmentation allows each transistor to specialize in one function, resolving the contradiction between speed and reliability.
Solution Approach 2:
The enhancement-mode transistor acts as an intermediary between the depletion-mode transistor and the external circuit. It controls the leakage current from the depletion-mode transistor in the off-state, enabling the depletion-mode transistor to maintain high-speed performance without suffering from high leakage.
2Reliability
If cascode configuration is used, then reliability and voltage blocking capability are improved, but ON-resistance increases
Solution Approach 1:
Different regions of the HEMT structure have different properties: the depletion-mode transistor region provides low resistance for high current handling, while the enhancement-mode transistor region provides high voltage blocking capability. This local differentiation resolves the contradiction between ON-resistance and voltage blocking.
3Strength
If depletion-mode transistor is used, then low resistance is achieved, but normally-on state causes control issues
Solution Approach 1:
The invention merges a depletion-mode transistor (normally-on, low resistance) with an enhancement-mode transistor (normally-off, high resistance) in a cascode configuration. The enhancement-mode transistor provides normally-off control while the depletion-mode transistor maintains low resistance, resolving the contradiction between resistance and controllability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The cascode configuration enhances reliability and longevity by maintaining low off-state current, reducing thermal stress, and improving high-frequency and high-power performance.
Implementation Method 1
This structure creates a two-dimensional electron gas at the interface of the materials, allowing electrons to move with very high mobility
Implementation Method 2
current limiting means arranged for ensuring that a drain source current of said HEMT structure, in an off-state of said HEMT structure, is at most 20 nA/mm
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A High Electron Mobility Transistor, HEMT, structure (1) having a gate (G), a source (S) and a drain (D), said HEMT structure comprising a depletion-mode transistor (3) having a breakdown voltage, current limiting means (9) arranged for ensuring that a drain source current of said HEMT structure, in an off-state of said HEMT structure, is at most 20 nA/mm, being a current per unit gate length of the depletion-mode transistor, wherein the HEMT structure may comprise a cascode configuration of said depletion-mode transistor with an enhancement mode transistor (6). The current limiting means may be embodied by a bleed resistor 9 that may additionally prevent the enhancement-mode transistor to enter avalanche. The bleed resistor may be connected between the gate terminal of the enhancement-mode transistor and the source terminal of the enhancement-mode transistor.