Cascode IC Combining D-Mode HEMT and E-Mode MOSFET Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current integrated circuits for power switching applications lack versatility and robustness, as they typically consist of either high-voltage e-mode or low-voltage d-mode components, limiting their adaptability to various current, voltage, and frequency conditions without modifying the internal architecture, and do not offer adjustable protection configurations.
Innovation Solution
An integrated circuit combining a high-voltage transistor in depletion mode with a low-voltage transistor in enhancement mode, allowing configuration as either a CASCODE or double-control circuit, with additional Kelvin connections and resistive passive components for enhanced protection and adaptability, facilitating wide-range application compatibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single high-voltage E-mode component is used, then the component can be controlled to switch on/off reliably, but the fabrication becomes complex and intrinsic performance decreases
Solution Approach 1:
The patent divides the single high-voltage E-mode component into two separate components: a high-voltage D-mode HEMT and a low-voltage E-mode MOSFET. This segmentation allows each component to be optimized for its specific voltage range and control characteristics, avoiding the fabrication complexity and performance degradation associated with creating a single high-voltage E-mode component.
Solution Approach 2:
The patent introduces an intermediary configuration where the high-voltage D-mode HEMT and low-voltage E-mode MOSFET are combined in a cascode or dual-control arrangement. This intermediary structure enables reliable switching control by using the MOSFET to control the HEMT, while maintaining simplified fabrication processes for each individual component.
2Reliability
If protection devices are added to control voltage during switching, then component reliability improves, but the circuit configuration becomes fixed and non-adjustable
Solution Approach 1:
The patent implements dynamic protection configuration by providing multiple selectable protection circuit arrangements that can be adjusted based on specific application requirements. The protection devices are configured to be selectable and adjustable, allowing users to optimize the protection level for different operating conditions while maintaining component reliability.
Solution Approach 2:
The patent creates a universal protection system that can adapt to various application scenarios. By incorporating selectable and adjustable protection configurations, the same integrated circuit can serve multiple functions and adapt to different voltage, current, and frequency conditions, enhancing both reliability and versatility.
3Reliability
If the integrated circuit is designed for specific voltage and current conditions, then optimization for those conditions is achieved, but adaptability to variable conditions is limited
Solution Approach 1:
The patent designs the integrated circuit with universal applicability by combining high-voltage and low-voltage components that can operate across a wide range of conditions. The circuit is optimized for specific conditions through selectable configurations while maintaining the capability to adapt to variable voltage, current, and frequency requirements, achieving both optimization and versatility.
Solution Approach 2:
The patent enables parameter changes and optimization by providing selectable protection configurations and control arrangements. Users can adjust circuit parameters such as protection levels, control modes, and operating points to optimize performance for specific applications while maintaining adaptability to variable conditions through the same integrated circuit.
Data Source
Figure 1a~1b
Figure 1c~1d
Figure 2a~2b
AI summary
The invention relates to an integrated circuit (3) comprising a housing (4) and a plurality of connection pins, a first chip (1) that includes a high-voltage depletion mode transistor, and a second chip (2) that includes a low-voltage enhancement mode transistor, the first chip and second chip each comprising a gate bump contact (13, 23), drain bump contact (11, 21) and source bump contact (12, 22); the source bump contact (12) of the high-voltage transistor being electrically connected to the drain bump contact (21) of the low-voltage transistor so as to form a central node of the circuit. The circuit includes at least one first Kelvin pin (36) that is electrically connected to the source bump contact (22) of the low-voltage transistor.